Publications

Journal Papers

  1. Y. Chen, H. Lan, B.H. Gwee, C. Qi, S.G. Razul and Z. Lin, “DQSA: Dynamic Quantized Self-Attention for Multi-task Encrypted Network Traffic Classification,” IEEE Transactions on Information Forensics and Security (Accepted), 2026.

  2. D. Cheng, Y.Y. Tee, X. Hong, T. Lin, Y. Shi and B.H. Gwee, “Unsupervised Domain Adaptation for IC Image Segmentation with Structural Constraint and Pseudo Supervision,” Microelectronic Engineering, v300, pp. 112373, Jun 2025.

  3. Y.Y. Tee, X. Hong, D. Cheng, T. Lin, Y. Shi and B.H. Gwee, “Integrated Circuit Image Synthesis for Unsupervised Circuit Annotation via Shape Consistent Image Translation,” IEEE Intelligent Systems, pp(99): 1-9, Jan 2025.

  4. X. Hong, Y.Y. Tee, Z. Hu, T. Lin, Y. Shi, D. Cheng and B.H. Gwee, “GNNReveal: A Novel Graph Neural Network-based Attack Method for IC Logic Gate De-Camouflaging,” IEEE Intelligent Systems, pp(99): 1-9, 2024.

  5. J.S. Ng, J. Chen, A.K. Nay, K.S. Chong and B.H. Gwee, “Securing against Side-Channel Attacks with Wide-Range in Situ Random Voltage Dithering on Async-logic AES Engine,” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, v32, n10, pp. 1959-1963, Oct 2024.

  6. Y.Y. Tee, D. Cheng, Y. Shi, T. Lin and B.H. Gwee, “Integrated Circuit Mask-GAN for Circuit Annotation with Targeted Data Augmentation,” IEEE Intelligent Systems, v39, n1, pp. 37-45, Jan/Feb 2024.

  7. X. Hong, T. Lin, Y. Shi and B.H. Gwee, “GraphClusNet: A Hierarchical Graph Neural Network for Recovered Circuit Netlist Partitioning,” IEEE Transactions on Artificial Intelligence, v4, n5, pp. 1199-1213, Oct 2023.

  8. Y.Y. Tee, X. Hong, D. Cheng, C.S. Chee, Y. Shi, T. Lin and B.H. Gwee, “Patch-based Adversarial Training for Error-aware Circuit Annotation of Delayered IC Images,” IEEE Transactions on Circuits and Systems II: Express Briefs, v70, n9, Sep 2023.

  9. Y.Y. Tee, X. Hong, D. Cheng, T. Lin, Y. Shi and B.H. Gwee, “Unsupervised Graph-based Image Clustering for Pretext Distribution Learning in IC Assurance,” Microelectronics Reliability, v148, 2023.

  10. J.S. Ng, J. Chen, K.S. Chong, J.S. Chang and B.H. Gwee, “A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic AES Accelerator Against Side-Channel Attacks,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v30, n9, pp. 1144-1157, Sep 2022.

  11. D. Cheng, Y. Shi, B.H. Gwee, T. Lin and K.A. Toh, “Delayered IC Image Analysis with Template-based Tanimoto Convolution and Morphological Decision,” IET Circuits, Devices and Systems, v16, n2, pp. 1144-1157, Mar 2022.

  12. T. Lin, Y. Shi, N. Shu, D. Cheng, X. Hong, J. Song and B.H. Gwee, “Deep learning-based image analysis framework for hardware assurance of digital integrated circuits,” Microelectronics Reliability, v123, n114196, pp. 1-17, Aug 2021.

  13. J. Chen, J.-S. Ng, K.-S. Chong, Z. Lin and B.H. Gwee, “A Novel Normalized Variance-based Differential Power Analysis against Masking Countermeasures,” IEEE Transactions on Information Forensics and Security, v16, pp. 3767-3779, Jun 2021.

  14. K.-S. Chong, J.S. Ng, J. Chen, N.K.Z. Lwin, N.A. Kyaw, W.G. Ho, J.S. Chang and B.H. Gwee, “Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, v11, n2, pp. 343-356, Jun 2021.

  15. W.G. Ho, K.-S. Chong, T.H. Kim, and B.H. Gwee, “A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection,” IEEE Transactions on Circuits and Systems II: Express Briefs, v68, n6, pp. 2122-2126, Jun 2020.

  16. W.G. Ho, K.-S. Chong, T.H. Kim, and B.H. Gwee, “A Secure Data-Toggling SRAM for Confidential Data Protection,” IEEE Transactions on Circuits and Systems I: Regular Paper, v66, n11, pp. 4186-4199, Nov 2019.

  17. A.A. Pammu, K.S. Chong, Yi Wang and B.H. Gwee, “A Highly Efficient Side Channel Attack with Profiling through Relevance Learning on Physical Leakage Information,” IEEE Transactions on Dependable Secure Computing, v16, n3, pp. 376-387, May/Jun 2019.

  18. A.A. Pammu, W.G. Ho, K. Z. L. Ne, K. S. Chong and B. H. Gwee, “A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor,” IEEE Transactions on Information Forensics and Security, v14, n4, pp. 1023-1036, Apr 2019.

  19. D. Cheng, Y. Shi, B.H. Gwee, T. Lin and K.A. Toh, “A Hierarchical Multi-Classifier System for Automated Analysis of Delayered IC Images,” IEEE Intelligent Systems, v39, n2, pp. 36-43, Mar/Apr 2019.

  20. D. Cheng, Y. Shi, T. Lin, B.H. Gwee and K.A.Toh, “Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images,” IEEE Transactions on Circuits and Systems II: Express Briefs, v65, n12, pp. 1849-1853, Dec 2018.

  21. W.G. Ho, K.-S. Chong, K.Z.L. Ne, and B.H. Gwee, “Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design,” IEEE Transactions on Very Large Scale Integration Systems, v26, n1, pp. 196-200, Jan 2018.

  22. C. Keer, V. Adrian, B.H. Gwee and J.S. Chang, “A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters,” IEEE Transactions on Circuits and Systems I: Regular Paper, v65, n1, pp. 394-405, Jan 2018.

  23. A.A. Pammu, K.-S. Chong and B.-H. Gwee, “A Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation,” Advances in Science, Technology and Engineering Systems Journal, v2, n3, pp. 420-426, 2017.

  24. K.S. Chong, W.G. Ho, T. Lin, B.H. Gwee, and J.S. Chang, “Sense-Amplifier Half-Buffer (SAHB): A Low Power High-Performance Asynchronous-Logic QDI Cell Template,” IEEE Transactions on Very Large Scale Integration Systems, v25, n2, pp. 402-415, Feb 2017.

  25. W.G. Ho, K.S. Chong, B.H. Gwee, and J.S. Chang, “Low Power Sub-Threshold Asynchronous QDI 32-Bit ALU based on Autonomous Signal-Validity Half-Buffer (ASVHB),” IET Circuits, Devices and Systems, v9, n4, pp. 309-318, Jul 2015.

  26. R. Zhou, K.S. Chong, B.H. Gwee and J.S. Chang, “A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA),” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v33, n7, pp. 989-1002, Jul 2014.

  27. J. Chen, K.S. Chong, B.H. Gwee, “Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing,” Circuits, Systems and Signal Processing, v33, n4, pp. 1-13, Apr 2014.

  28. K.L. Chang, J.S. Chang, B.H. Gwee, K.S. Chong, “Synchronous-logic and Asynchronous-logic 8051 Microcontroller Cores for Powering the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, v3, n1, pp. 23-34, Mar 2013.

  29. T. Lin, K.S. Chong, J.S. Chang and B.H. Gwee, “An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks,” IEEE Journal of Solid State Circuits, v48, n2, pp. 573-586, Feb 2013.

  30. K.S. Chong, K.L. Chang, B.H. Gwee and J.S. Chang, “Synchronous-logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors,” IEEE Journal of Solid State Circuits, v47, n3, pp. 769-780, Mar 2012.

  31. C.F. Law, B.H. Gwee and J.S. Chang, “Modeling and Synthesis of Asynchronous Pipelines,” IEEE Transactions on Very Large Scale Integration Systems, v19, n4, pp. 682-695, April 2011.

  32. Y. Shi, B.H Gwee and J. Chang, “Asynchronous DSP for Low-power Energy-efficient Embedded Systems,” Microprocessors and Microsystems, v35, n1, pp. 318–328, 13 Feb 2011.

  33. V. Adrian, J.S. Chang and B.H. Gwee, “A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters,” IEEE Transactions on Circuits and Systems I: Regular Paper, v59, n9, pp. 2320–2333, Sep 2010.

  34. B.H. Gwee, J.S. Chang, Y. Shi, C.C. Chua and K.S. Chong, “A Low-Voltage Micropower Asynchronous Multiplier with Shift-Add Multiplication Approach,” IEEE Transactions on Circuits and Systems I: Regular Paper, v56, n7, pp. 1349-1359, July 2009.

  35. V. Adrian, J.S. Chang and B.H. Gwee, “A Low Voltage Micropower Digital Class D Amplifier Modulator for Hearing Aids,” IEEE Transactions on Circuits and Systems I: Regular Paper, v56, n2, pp. 337-349, Feb 2009.

  36. B.H. Gwee and J.S. Chang, “An Efficient Hybrid Genetic Hill-climbing Algorithm for Solving n-region 4-coloring Map Problems,” Far East Journal of Experimental and Theoretical Artificial Intelligence, v1, n2, pp. 151-178, 2008.

  37. C.F. Law, B.H. Gwee and J.S. Chang, “Asynchronous Control Network Optimization Using Fast Minimum Cycle Time Analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, v27, n6, pp. 985-998, Jun 2008.

  38. K.S. Chong, B.H. Gwee and J.S. Chang, “Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors,” IEEE Journal of Solid State Circuits, v42, n9, pp. 2034-2045, Sep 2007.

  39. C.F. Law, B.H. Gwee and J.S. Chang, “Fast and memory-efficient Invariant Computation of Ordinary Petri Nets,” IET Proceedings on Computers & Digital Techniques, vol. 1, no. 5, pp. 612-624, Sep 2007.

  40. K.S. Chong, B.H. Gwee, and J.S. Chang, “Design of Several Asynchronous-Logic Macrocells for a Low-Voltage Micropower Cell Library,” IET Proceedings on Circuits, Devices and Systems, vol. 1, no. 2, pp. 161-169, Apr 2007.

  41. K.S. Chong, B.H. Gwee, and J.S. Chang, “Low Energy 16-bit Booth Leapfrog Array Multiplier using Dynamic Adders,” IET Proceedings on Circuits, Devices and Systems, vol. 1, no. 2, pp. 170-174, Apr 2007.

  42. K.S. Chong, B.H. Gwee and J.S. Chang, “A 16-Channel Low Power Non-Uniform Spaced Filter Bank Core for Digital Hearing Aids,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 9, pp. 853-857, 2006.

  43. B.H. Gwee, J.S. Chang and V. Adrian, “A Micropower Low Distortion Digital Class D Amplifier based on an Algorithmic Pulse Width Modulator,” IEEE Transactions on Circuits and Systems I: Regular Paper, vol. 52, no. 10, pp. 2007-2022, Oct 2005.

  44. B.H. Gwee and M.H. Lim, “An Evolution Search Algorithm for Solving N-queen Problems,” International Journal of Computer Applications in Technology, vol. 24, No. 1, pp. 43-48, Jun 2005.

  45. K.S. Chong, B.H. Gwee and J.S. Chang, “A Micropower Low-Voltage Low Power Multiplier with Reduced Spurious Switching,” IEEE Transactions on Very Large Scale Integration Systems, vol. 13, no. 2, pp. 255-265, Feb 2005.

  46. M.T. Tan, J.S. Chang, H.C. Chua and B.H. Gwee, “An Investigation into the Parameters Affecting THD in Low-voltage Low-Power Class D Amplifier,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, no. 10, pp. 1304-1315, Oct 2003.

  47. B.H. Gwee and J.S. Chang, “A Novel Delta-Compensation Sampling Process for Digital Class D Amplifiers,” Electrical and Electronic Engineering Research, pp. 24-25, 2003.

  48. B.H. Gwee, J.S. Chang and H.Y. Li, “A Micropower Low-Distortion Digital Pulsewidth Modulator for a Digital Class D Amplifier,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 4, pp. 245-256, Apr 2002.

  49. B.H. Gwee and M.H. Lim, “Flexible IC Floorplan Design with Genetic Algorithm,” Electrical and Electronic Engineering Research, pp. 22-23, 2000.

  50. B.H. Gwee and M.H. Lim, “A GA with Heuristic Based Decoder for IC Floorplanning,” Integration, the VLSI Journal, vol. 28, no. 2, pp. 157-172, 1999.

  51. B.H. Gwee, M.H. Lim and B.H. Soong, “Self-adjusting Diagnostic System for the Manufacture of Crystal Resonators,” IEEE Transactions on Industry Applications, vol. 32, no. 1, pp. 73-79, Jan/Feb 1996.

  52. B.H. Gwee and M.H. Lim, “Polyominoes Tiling by a Genetic Algorithm,” Computational Optimization and Applications, vol. 6, pp. 273-291, Nov 1996.

  53. M.H. Lim, S. Rahardja and B.H. Gwee, “A GA Paradigm for Learning Fuzzy Rules,” Fuzzy Sets and Systems, vol. 82, pp. 177-186, Sep 1996.

  54. M.H. Lim, B.H. Gwee and Y. Kawada, “Intelligent Monitoring of Frequency Trimming Process,” Journal of Intelligent Manufacturing, vol. 4, pp. 375-383, 1993.

Patents

  1. K.S. Chong, B.H. Gwee, W.G. Ho and N.K.Z. Lwin, “Integrated Circuit Layout Cell, Integrated Circuit Layout Arrangement, and Methods of Forming the Same,” US Patent No. US 11,695,011 B2, filed on 2 May 2018, Granted on 4 July 2023.

  2. K.S. Chong, B.H. Gwee and A. A. Pammu, “Hardware Security to Countermeasure Side-Channel Attacks,” US Patent No. 11,227,071 B2, filed on 19 Mar 2018, Granted on 18 Jan 2022.

  3. K.S. Chong, B.H. Gwee, W.G. Ho and N.K.Z. Lwin, “Camouflage Digital Cells To Prevent Reverse Engineering,” PCT US Patent Applications and Singapore provisional Patent Application No. 10201803673Y, 2 May 2018.

  4. J.S. Chang, B.H. Gwee and K.S. Chong, “Digital Cell,” US Patent No. US 8,994,406 B2, filed on 19 Dec 2012, Granted on 31 Mar 2015.

Book Monograph

  1. H. Li and B.H. Gwee, Digital Pulse Width Modulator, ISBN 978-3-639-17876-0, VDM Publishing House Ltd. 2009.

Book Chapters

  1. D. Cheng, Y. Shi, T. Lin and B.H. Gwee, “Domain-Integrated Machine Learning for IC Image Analysis,” in Fusion of Machine Learning Paradigms, Springer Nature, 2023.

  2. K.S. Chong, T. Lin, W.G. Ho, B.H. Gwee and J.S. Chang, “Asynchronous Circuits for Dynamic Voltage Scaling, in Asynchronous Circuit Applications, IET Press, 2019.

  3. B.H. Gwee and K.S. Chong, “Low Power Asynchronous Circuit Design – An FFT/IFFT Processor,” in CMOS Nanoelectronics, kris iniewski (Ed.), 2010.

  4. B.H. Gwee and J.S. Chang, “A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems,” in Design and Application of Hybrid Intelligent Systems, A. Abraham, M. Köppen, K. Franke (Eds.), IOS Press, pp. 252-261, 2003.

Conference Papers

  1. Y. Chen, W. Zheng, B. H. Gwee, Q. Cao, S. G. Razul, and Z. Lin, “UniOOD: A Unified Framework for Domain Generalization and Out-of-Distribution Detection in Time Series,” IEEE International Symposium on Circuits and Systems (ISCAS), 2026.

  2. J. Dai, D. Cheng, X. Wang, F. Ji, Y. Shi, and B. H. Gwee, “ICNet: Cross-Modality Image Analysis for IC Localization in Printed Circuit Boards,” IEEE International Symposium on Circuits and Systems (ISCAS), 2026.

  3. Z. Long, J. Chen, H. Zhang, T. Lin, A. K. Nay, and B. H. Gwee, “RASLL: A Removal Attack on SAT-Resistant Logic Locking,” IEEE International Symposium on Circuits and Systems (ISCAS), 2026.

  4. Z. Long, H. Zhang, J. Chen, T. Lin, B. H. Gwee, “InvMUX: Cascaded Inverter-MUX-Based Logic Locking Against Machine Learning Attacks,” ICDIS ‘25: Proceedings of the 2nd International Symposium on Integrated Circuit Design and Integrated System, pp 45 – 49, Singapore, 22-24 Nov, 2025.

  5. J. Dai, D. Cheng, X. Wang, F. Ji, Y. Shi, and B.-H. Gwee, “ICNet: Multi-modality Image Analysis for IC Localization in Printed Circuit Boards,” IEEE Workshop on Signal Processing Systems (SiPS) 2025, under review.

  6. T. Lan, Y. Wang, F. Ji, X. Wang, D. Cheng, Y. Shi, and B.-H. Gwee, “GraphPCB: Graph-encoded Printed Circuit Board Datasets for Component Classification with Graph Neural Networks,” The Thirty-Ninth Annual Conference on Neural Information Processing Systems (NeurlPS 2025), under review.

  7. X. Wang, D. Cheng, Y. Shi, and B.-H. Gwee, “Multi-Orientation OCR Pipeline for IC Printed Mark Recognition,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Penang, Malaysia, 5-8 Aug 2025.

  8. J. Lee, V. Adrian, K. S. Tantra, B.H. Gwee and J.S. Chang, “A Novel Energy-Efficient Continuous-Time Hysteretic VCO-Based Comparator,” IEEE International Symposium on Circuits and Systems (ISCAS 2025), London, 25–28 May 2025.

  9. Y. Wang, X. Wang, D. Cheng, T. Lin, F. Ji, Y. Shi and B.-H. Gwee, “SSRNet: Few-Shot IC Segmentation in Automated PCB Image Processing,” IEEE International Symposium on Circuits and Systems (ISCAS 2025), London, 25–28 May 2025.

  10. H. Zhang, X. Hong, S. Sheng, J. Cheng, A.K. Nay, K.-S. Chong, Z. Lin and B.-H. Gwee, “N-MUX: Neighborhood-Based Logic Locking Against Machine Learning Attacks,” IEEE International Symposium on Circuits and Systems (ISCAS 2025), London, 25– 28 May 2025.

  11. X. Ma, Y. Li, F. Ji, T. Lin, Y. Shi, D. Cheng and B.-H. Gwee, “Multiple Hypothesis Testing for SEM Image Processing: A Case Study on Standard Cell Partition.” IEEE International Symposium on Circuits and Systems (ISCAS 2025), London, 25-28 May 2025.

  12. H. Zhang, T. Lin, F. Ji, D. Cheng, Y. Shi and B.-H. Gwee, “Long-Short-GNN: A Novel Graph Neural Network for Detecting FPGA IP Circuits for Hardware Assurance,” IEEE International Symposium on Circuits and Systems (ISCAS 2025), London, 25– 28 May 2025.

  13. Y.J. Ng, Y.Y. Tee, D. Cheng, and B.H. Gwee, “SAMIC: Segment Anything Model for Integrated Circuit Image Analysis,” IEEE Region 10 Conference (IEEE TENCON 2024), Singapore, 1-4 Dec 2024.

  14. J. Lee, V. Adrian, Y. Xie, B.H. Gwee and J.S. Chang, “A Novel Energy-Efficient RF VCO-ADC with an Intrinsic Quasi-sinc3 Anti-Aliasing Filter,” International Conference on Imaging Systems and Techniques (IST 2024), IEEE International Conference on Electronics, Circuits and Systems (ICECS), Nancy, France, 18-20 Nov 2024.

  15. S. Sheng, K.S. Chong, J.S. Ng, Z. Lin, B. H. Gwee “A High-Accuracy and Energy-Efficient Spiking Neural Network with On-FPGA STDP Learning Based on Asynchronous CORDIC,” Asia Pacific Conference on Circuits and Systems (APCCAS), Taipei, Taiwan, 7-9 Nov 2024.

  16. J. Lee, V. Adrian, B.H. Gwee and J.S. Chang, “A Novel Voltage-Controlled Oscillator Linearized by a Resistorless Dynamic-Degeneration Technique,” Asia Pacific Conference on Circuits and Systems (APCCAS), Taipei, Taiwan, 7-9 Nov 2024.

  17. D. Cheng, J. Dai, Y.-Y. Tee, Y. Shi, and B.-H. Gwee, “PCB Surface Component Detection with Computer Vision Assisted Label Generation,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 15-18 July 2024.

  18. L. Li, D. Cheng, Y. Shi and B.H. Gwee, “Unpaired Synthesis of IC Scanning Electron Microscopy Images with Structural Constraints,” International Conference on Imaging Systems and Techniques (IST 2024), Tokyo, Japan, 14-16 Oct 2024.

  19. J. Chen, H. Zhang and B.H. Gwee, “A Novel Non-Profiling Side-Channel Attack on Masked Devices with Connectivity Matrix,” IEEE International Symposium on Circuits and Systems (ISCAS 2024), Singapore, 19– 22 May 2024.

  20. Y. Tong, Y. Chen, B.H Gwee, C. Qi, S.G. Razul, and Z. Lin, “A method for out-of-distribution detection in encrypted mobile traffic classification,” IEEE International Symposium on Circuits and Systems (ISCAS 2024), Singapore, 19– 22 May 2024.

  21. X. Hong, Y.Y. Tee, T. Lin, H. Zhang, Y. Shi, and B.H. Gwee, “MLConnect: a Machine Learning Based Connection Prediction Framework for Error Correction in Recovered Circuit,” IEEE International Symposium on Circuits and Systems (ISCAS 2024), Singapore, 19– 22 May 2024.

  22. J. Chen, H. Liu, J.S. Ng, N.A. Kyaw, K.S. Chong, Z. Lin and B.H. Gwee, “Non-profiling Time-Frequency Analysis based Correlation Optimization with Deep Learning,” IEEE Conference on Industrial Electronics and Applications (ICIEA), Ningbo, China, 18 - 22 August 2023.

  23. Chen, Yongming, Yuzhou Tong, Gwee Bah Hwee, Qi Cao, Sirajudeen Gulam Razul, and Zhiping Lin. “Encrypted mobile traffic classification with a few-shot incremental learning approach.” IEEE Conference on Industrial Electronics and Applications (ICIEA), Ningbo, China, 18 - 22 August 2023.

  24. S. Wu, S. Sheng, J. S. Ng, J. Chen, Z. Zou, K. S. Chong, Z. Lin, B. H. Gwee, “A Power-Efficient LIF Neuron Implementation for Event-Driven Spiking Neural Networks,” IEEE Conference on Industrial Electronics and Applications (ICIEA), Ningbo, China, 18 - 22 August 2023.

  25. X. Hong, Y.Y. Tee, T. Lin, Y. Shi, D. Cheng, E. Huang, and B.H. Gwee, “GoCLIP: Graph one-class CLassification for Intellectual Property Circuit Identification,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2023), Penang, Malaysia, 24-27 July 2023.

  26. Y.Y. Tee, C.S. Chee, D. Cheng, X. Hong, Y. Shi, and B.H. Gwee, “A Strategic Framework for Evaluating Data Augmentation in Microscopic IC Image Analysis,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2023), Penang, Malaysia, 24-27 July 2023.

  27. D. Cheng, Y. Shi, Y.Y. Tee, J. Song, X. Wang, B. Wen and B.-H. Gwee, “Deep-learning-Based X-Ray CT Slice Analysis for Layout Verification in Printed Circuit Boards,” IEEE International Conference on Artificial Intelligence Circuits & Systems (AICAS), Hangzhou, China, 11-13 Jun 2023.

  28. T. Lin, Y. Shi and B.H. Gwee, “SEM2GDS: A Deep-Learning Based Framework to Detect Malicious Modifications in IC Layout,” IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, California, USA, 21– 25 May 2023.

  29. J. Lee, V. Adrian, S.Y. Tay, J.S. Chang, Y. Xie and B.H. Gwee, “A 3D-Printed Fourth-Order Stacked Filter for Integrated DC-DC Converters,” IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, California, USA, 21– 25 May 2023.

  30. Y. Chen, Y. Tong, B.H. Gwee, Q. Cao, S.G. Razul and Z. Lin, “Real-Time Traffic Classification in Encrypted Wireless Communication Network,” IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, California, USA, 21– 25 May 2023.

  31. Z. Lin, Y. Chen, B.H. Gwee, Q. Cao, G.R. Sirajudeen, Y. Tong and J. Chen, “Real-Time Traffic Classification in Encrypted Wireless Communication Network,” IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, California, USA, 21– 25 May 2023.

  32. J.S. Ng, J. Chen, S. Wu, N.A. Kyaw, K.S. Chong and B.H. Gwee, “Improving FPGA-Based Async-Logic AES Accelerator with the Integration of Sync-Logic Block Rams,” IEEE International Symposium on Circuits and Systems (ISCAS 2023), Monterey, California, USA, 21– 25 May 2023.

  33. J. Chen, J.S. Ng, N.A. Kyaw, Z. Zou, K.S. Chong, Z. Lin, B.H. Gwee, “Incremental Linear Regression Attack,” Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022), Singapore, 14-16 Dec 2022.

  34. Y.Y. Tee, D. Cheng, C.S. Chee, T. Lin, Y. Shi, and B.H. Gwee, “Unsupervised Domain Adaptation with Histogram-gated Image Translation for Delayered IC Image Analysis,” IEEE International Conference on Physical Assurance and INspection of Electronics (PAINE 2022), Alabama, USA, 25 – 27 Oct 2022.

  35. D. Cheng, Y.Y. Tee, J. Song, Y. Shi, T. Lin, and B.H. Gwee, “Semantic-Masked Intensity Augmentation for Deep Learning-based Analysis of FPGA Images,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2022), Singapore, 18 Jul – 20 Jul 2022.

  36. Y.Y. Tee, X. Hong, D. Cheng, T. Lin, Y. Shi, and B.H. Gwee, “Hybrid Unsupervised Clustering for Pretext Distribution Learning in IC Image Analysis,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2022), Singapore, 18 Jul – 20 Jul 2022.

  37. J.S. Ng, W.G. Ho, K.S. Chong and B.H. Gwee, “An Asynchronous-Logic Masked Advanced Encryption Standard (AES) Accelerator and its Side-Channel Attack Evaluations,” IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, Texas, USA, 28 May – 1 Jun 2022.

  38. J. Chen, J.S. Ng, N.A. Kyaw, N.K.Z. Lwin, K.S. Chong, B.H. Gwee, J.S. Chang, Z. Lin, “Non-profiling based Correlation Optimization Deep Learning Analysis,” IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, Texas, USA, 28 May – 1 Jun 2022.

  39. S.Y. Tay, V. Adrian, J.C. Chang, J. Lee, and B.H. Gwee, “A Versatile and Accurate Vector-Based Method for Modeling and Analyzing Planar Air-Core Inductors,” IEEE International Symposium on Circuits and Systems (ISCAS 2022), Austin, Texas, USA, 28 May – 1 Jun 2022.

  40. L. Huang, D. Cheng, X. Yang, T. Lin, Y. Shi, K. Yang, B.H. Gwee, and B. Wen, “Joint Anomaly Detection and Inpainting for Microscopy Images via Deep Self-Supervised Learning,” in IEEE International Conference on Image Processing (ICIP 2021), Alaska, USA, 19-21 Sep 2021.

  41. X. Hong, Y. Shi, T. Lin and B.H. Gwee, “ASIC Circuit Netlist Recognition Using Graph Neural Network,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA 2021), Sep 2021.

  42. J. Chen, J.S. Ng, N.A. Kyaw, N.K.Z. Lwin, W.G. Ho, K.S. Chong, B.H. Gwee, J.S. Chang, Z. Lin, “Normalized Differential Power Analysis - A Ghost Peak Suppressing Differential Power Analysis,” IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, South Korea, 22-28 May 2021.

  43. W.G. Ho, A. A. Pammu, N.K.Z. Lwin, K.S. Chong and B.H. Gwee, “High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications,” IEEE International Systems-On-Chip Conference (ISOCC 2020), Yeosu, Korea, 21-24 Oct 2020.

  44. T. Lin, Y. Shi, N. Shu, D. Cheng, X. Hong, J. Song and B.H Gwee, “Deep Learning-Based Image Analysis Framework for Hardware Assurance of Digital Integrated Circuits,” IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), Singapore, 20-23 July 2020.

  45. J.S. Ng, W.G. Ho, K.S. Chong and B.H. Gwee, “A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES),” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2020, Seville, Spain, 17-20 May 2020.

  46. W.G. Ho, K.S. Chong, T.H. Kim and B.H. Gwee, “A Secure Data-Toggling SRAM for Confidential Data Protection,” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2020, Seville, Spain, 17-20 May 2020.

  47. W.G. Ho, N.K.Z. Lwin, K.S. Chong and B.H. Gwee, “A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications,” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2020, Seville, Spain, 17-20 May 2020.

  48. K.S. Chong, A. Shreedhar, K.Z.L. Ne, A.K. Nay, W.G. Ho, C. Wang, J. Zhou, B.H. Gwee and J. Chang, “Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells,” Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Xi’an, China, Dec 2019.

  49. W.G. Ho, A. A. Pammu, N.K.Z. Lwin, K.S. Chong and B.H. Gwee, “Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications,” 32nd IEEE International Systems-On-Chip Conference (SOCC), Singapore, Sep 2019.

  50. D. Cheng, Y. Shi, T. Lin, B.H. Gwee and K.A.Toh, “Global Template Projection and Matching Method for Training-free Analysis of Delayered IC Images,” IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019.

  51. A.R. Shreedhar, K.S. Chong, N.K.Z. Lwin, N.A. Kyaw, L. Nalangilli, W. Shu, J.S. Chang and B.H. Gwee, “Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design,” IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019.

  52. X. Hong, D. Cheng, Y. Shi, T. Lin and B.H. Gwee, “Deep Learning for Automatic IC Image Analysis,” IEEE International Conference on Digital Signal Processing (DSP), Shanghai, China, Nov 2018.

  53. W.G. Ho, Z. Zheng, K.S. Chong and B.H. Gwee, “A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation,” IEEE 23rd International Conference on Digital Signal Processing (DSP), Shanghai, China, Nov 2018.

  54. D. Cheng, Y. Shi, T. Lin, B.H. Gwee and K.A.Toh, “Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images,” IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.

  55. W.G. Ho, K.S. Chong, K. Z. L. Ne, B.H. Gwee and J.S. Chang, “Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design,” IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018.

  56. C. Keer, V. Adrian, B.H. Gwee and J.S. Chang, “A Low-Harmonics Low-Noise Randomized Modulation Scheme for Multi-Phase DC-DC Converters,” IEEE International NEWCAS Conference, Strasbourg, France, June 2017.

  57. W.G. Ho, K.S. Chong, B.H. Gwee and J.S. Chang, “Low-Power High Speed Robust Asynchronous-Logic QDI Sense Amplifier Half-Buffer Circuits for Power Management Applications,” IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, USA, May 2017.

  58. A. A. Pammu, K.-S. Chong and B.-H. Gwee, “Highly Secured State-shift Local Clock Circuit to Countermeasure against Side Channel Attack,” IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, USA, May 2017.

  59. Q. Liu, V. Adrian, B.H. Gwee and J.S. Chang, “A Class-E RF Power Amplifier with a Novel Matching Network for High-Efficiency Dynamic Load Modulation,” IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, USA, May 2017.

  60. J. Lim, W.G. Ho, K.S. Chong, B.H. Gwee and J.S. Chang, “DPA-Resistant QDI Dual-Rail AES S-Box Based on Power-Balanced Weak-Conditioned Half-Buffer,” IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, USA, May 2017.

  61. A. A. Pammu, K.-S. Chong and B.-H. Gwee, “Highly Secured Arithmetic Hiding based S-Box on AES-128 Implementation,” International Symposium on Integrated Circuits (ISIC), (Best Student Paper Award), Singapore, Dec 2016.

  62. Q. Liu, V. Adrian, B.H Gwee and J.S. Chang, “A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network,” International Symposium on Integrated Circuits (ISIC), Singapore, Dec 2016.

  63. A. A. Pammu, K.-S. Chong, K. Z. L. Ne, W.-G. Ho, N. Liu and B.-H. Gwee, “Success Rate Model for Fully AES-128 in Correlation Power Analysis,” Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, Oct 2016.

  64. A. A. Pammu, K.-S. Chong, W.-G. Ho and B.-H. Gwee, “Interceptive Side Channel Attack on AES-128 Wireless Communications for IoT Applications,” Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, Oct 2016.

  65. A. A. Pammu, K.S. Chong and B.H. Gwee, “Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture,” IEEE International Conference on Networking, Architecture, and Storage (NAS), (Best Presentation Award), California, USA, Aug 2016.

  66. W.G. Ho, N. Liu, K.Z.L. Ne, K.S. Chong, B.H. Gwee and J.S. Chang, “High Performance Low Overhead Template-Based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits,” IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016.

  67. W.G. Ho, K.Z.L. Ne, N.P. Srinivas, K.S. Chong, T.H. Kim and B.H. Gwee, “Area-Efficient and Low Stand-by Power 1K-Byte Transmission-Gate-Based Non-Imprinting High-Speed Erase (TNIHE) SRAM,” IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 2016.

  68. N. Liu, K.S. Chong, W.G. Ho, B.H. Gwee and J.S. Chang, “Low Normalized Energy Derivation Asynchronous Circuit Synthesis Flow through Fork-Join Slack Matching for Cryptographic Applications,” Design, Automation and Test in Europe (DATE), March 2016.

  69. K.S. Chong, K.Z.L. Ne, W.G. Ho, N. Liu, A. Akbar, B.H. Gwee and J.S. Chang, “Counteracting Differential Power Analysis: Hiding Encrypted Data from Circuit Cells,” IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), (Invited Paper), Singapore, June 2015.

  70. H. Yin, B.H. Gwee, Z. Lin, A. Kumar, S.G. Razul and C.M.S. See, “Novel Real-Time System Design for Floating-point Sub-Nyquist Multi-Coset Signal Blind Reconstruction,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 954-957, Lisbon, Portugal, May 2015.

  71. W.G. Ho, K.S. Chong, B.H. Gwee, and J.S. Chang, “High Robustness Energy- and Area-Efficient Dynamic-Voltage-Scaling 4-phase 4-rail Asynchronous-Logic Network-on-Chip (ANoC),” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1913-1916, Lisbon, Portugal, May 2015.

  72. R. Zhou, K.S. Chong, T. Lin, B.H. Gwee, and J.S. Chang, “A Single-VDD Half-Clock-Tolerant Fine-Grained Dynamic Voltage Scaling Pipeline,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2589-2592, Lisbon, Portugal, May 2015.

  73. W.G. Ho, K.S. Chong, B.H. Gwee, J.S. Chang and K.Z.L. Ne, “A Dynamic-Voltage-Scaling 1kbyte×8-bit Non-Imprinting Master-Slave SRAM with High Speed Erase for Low-Power Operation,” International Symposium on Integrated Circuits (ISIC), pp. 320-323, Singapore, Dec 2014.

  74. T.S. Ng, Y. Sun, V. Adrian, B.H Gwee, and J.S. Chang, “Design of an Output Stage for High Switching Frequency DC-DC Converters,” International Symposium on Integrated Circuits (ISIC), pp. 488-491, Singapore, Dec 2014.

  75. S. Nashit, V. Adrian, K. Cui, Q.A. Mai, B.H. Gwee, and J.S. Chang, “A Self-Oscillating Class D Audio Amplifier with Dual Voltage and Current Feedback,” International Symposium on Integrated Circuits (ISIC), pp. 480-483, Singapore, Dec 2014.

  76. W.G. Ho, K.S. Chong, B.H. Gwee, and J.S. Chang, “Low Delay-Variation Sub-/Near-Threshold Asynchronous-to-Synchronous Interface Controller for GALS Network-on-Chips,” IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 5-8, Ishigaki, Japan, Nov 2014.

  77. V. Adrian, C. Keer, B.H. Gwee and J.S. Chang, “A Randomized Modulation Scheme for Filterless Digital Class D Audio Amplifiers,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 774-777, Melbourne, Australia, June 2014.

  78. R. Zhou, K.S. Chong, B.H. Gwee, J.S. Chang and W.G. Ho, “Synthesis of Asynchronous QDI Circuits using Synchronous Coding Specifications,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 153-156, Melbourne, Australia, June 2014.

  79. Y. Shi and B.H. Gwee, “Designing Globally-Asynchronous-Locally-Synchronous System from Multi-Rate Simulink Model,” IEEE New Circuits and Systems Conference (NEWCAS), pp. 1-4, Paris, France, June 2013.

  80. W.G. Ho, K.S. Chong, B.H. Gwee and J.S. Chang, “Low Power Sub-Threshold Asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-Bit ALU,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 353-356, Beijing, China, May 2013.

  81. K.L Chang, K.S. Chong, B.H. Gwee and J.S. Chang, “A Dual-Core 8051 Microcontroller System Based on Synchronous-Logic and Asynchronous-Logic,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3022-3025, Beijing, China, May 2013.

  82. T. Lin, K.S. Chong, J.S. Chang, and B.H. Gwee, “A Robust Asynchronous Approach for Realizing Ultra-Low Power Digital Self-Adaptive VDD Scaling System,” IEEE Subthreshold Microelectronics Conference (SubVt), pp. 1-3, Waltham, USA, (Best Student Paper Award), Oct 2012.

  83. Y. Shi, B.H. Gwee, Y. Ren, T.K. Phone and C.W. Ting, “Extracting Functional Modules from Flattened Gate-Level Netlist,” International Symposium on Communications and Information Technologies (ISCIT), pp. 538-543, Gold Coast, Australia, Oct 2012.

  84. K.L Chang, K.S. Chong, B.H. Gwee and J.S. Chang, “A Comparative Study on Asynchronous Quasi-Delay-Insensitive Templates,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1819-1822, Seoul, Korea, May 2012.

  85. W.G. Ho, K.S. Chong, T. Lin, B.H. Gwee and J.S. Chang, “Energy-Delay Efficient Asynchronous-Logic 16x16-Bit Pipelined Multiplier Based on Sense Amplifier-Based Pass Transistor Logic,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 492-495, Seoul, Korea, May 2012.

  86. J. Chen, K.S. Chong, B.H. Gwee and J.S. Chang, “An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability in 65 nm CMOS,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1835-1838, Seoul, Korea, May 2012.

  87. R. Zhou, K.S. Chong, B.H. Gwee, and J.S. Chang, “Quasi-Delay-Insensitive Compiler: Automatic Synthesis of Asynchronous Circuits from Verilog Specifications,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 1-4, Seoul, Korea, Aug 2011.

  88. W.G. Ho, K.S. Chong, B.H. Gwee, J. Chang and M.F. Yee, “A power-efficient integrated input/output completion detection circuit for asynchronous-logic quasi-delay-insensitive Pre-Charged Half-Buffer,” International Symposium on Integrated Circuits (ISIC), pp. 376 - 379, Singapore, Dec 2011.

  89. J. Chen, K.S. Chong, B.H. Gwee and J.S. Chang, “A Low-Power Dual-Rail Inputs Write Method for Bit-Interleaved Memory Cells,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 325-328, Rio de Janeiro, Brazil, May 2011.

  90. W.G. Ho, K.S. Chong, B.H. Gwee, J.S. Chang, Y. Sun, K.L. Chang, “Improved Asynchronous-Logic Dual-Rail Sense Amplifier-Based Pass Transistor Logic with High Speed and Low Power Operation,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1936-1939, Rio de Janeiro, Brazil, May 2011.

  91. Y. Ren, Y. Shi, B.H. Gwee and C.W. Ting, “An Efficient VLSI Circuit Extraction Algorithm for Transistor-level to Gate-level Abstraction,” Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 49-52, Shanghai, China, Sep 2010.

  92. Y. Ren, Y. Shi and B.H. Gwee, “A Novel Gate-level to Behavior-level Conversion Algorithm with High Microcell Identification Rate,” IASTED International Conference on Circuits and Systems, vol. 712, pp. 138, Maui, Hawaii, USA, Aug 2010.

  93. J. Chen, K.S. Chong, B.H. Gwee and J.S. Chang, “An Ultra-Low Power Asynchronous Quasi-Delay-Insensitive (QDI) Sub-Threshold Memory with Bit-Interleaving and Completion Detection,” IEEE International NEWCAS Conference, Montreal, Canada, pp. 117–120, June 2010.

  94. T. Lin, K.S. Chong, B.H. Gwee, J.S. Chang and Z. Qiu, “Analytical Delay Variation Modeling for Evaluating Sub-Threshold Synchronous/Asynchronous Designs,” IEEE International NEWCAS Conference, Montreal, Canada, pp. 69-72, June 2010.

  95. Y. Shi, C.W. Ting, B.H. Gwee and Y. Ren, “A Highly Efficient Method for Extracting FSMs from Flattened Gate-Level Netlist,” IEEE International Symposium on Circuits and Systems (ISCAS), Paris, France, pp. 2610-2613, May 2010.

  96. T. Ge, J.S. Chang and B.H. Gwee, “Power Supply Noise in High Power-Efficient Open-Loop Class D Amplifiers for Hearing Aid,” IEEE-NIH Circuits and Systems for Medical and Environmental Applications Workshop, Merida, Mexico, Dec 2009.

  97. N.K. King, J. Liu, K.K. Lee, J.S. Chang, B.H. Gwee, B.T. Ang, “Optimizing Outcome Prediction in Severe Head Injury Using a Two-stage Logistic Regression Method,” World Federation of Neurosurgical Societies Meeting (WFNS), Boston, USA, Aug 2009.

  98. V. Adrian, J.S. Chang, B.H. Gwee, and S. Tedjaseputro, “Spectral Analysis of Randomized Switching Frequency Modulation Scheme with a Triangular Distribution for DC-DC Converters,” International Conference of COMPUTING in Engineering, Science and Informatics (ICC), pp. 119-122, California, USA, Apr 2009.

  99. K.L. Chang, B.H. Gwee and Y.J. Zhang, “A Performance Benchmark on Asynchronous Matched-Delay Templates,” IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, pp. 1008-1011, May 2009.

  100. T. Lin, K.S. Chong, B.H. Gwee and J. Chang, “Fine-Grained Power Gating for Leakage and Short-Circuit Power Reduction by Using Asynchronous-Logic,” IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan, pp. 3162-3165, May 2009.

  101. K.L. Chang, B.H. Gwee and Y.J. Zhang, “A Semi-Custom Memory Design for an Asynchronous 8051 Microcontroller,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3398-3401, Seattle, USA, May 2008.

  102. K.L. Chang, Y. Zhu and B.H. Gwee, “De-synchronization of a Point-of-Sales Digital Logic Controller,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3402-3405, Seattle, USA, May 2008.

  103. K.S. Chong, B.H. Gwee and J.S. Chang, “A simple methodology of designing asynchronous circuits using commercial IC design tools and standard library cells,” International Symposium on Integrated Circuits (ISIC), pp. 176-179, Singapore, Sep 2007.

  104. V. Adrian, B.H. Gwee and J.S. Chang, “A Review of Design Methods for Digital Modulators,” International Symposium on Integrated Circuits (ISIC), pp. 85-88, Singapore, Sep 2007.

  105. K.S. Chong, B.H. Gwee and J.S. Chang, “A Low Energy FFT/IFFT Processor for Hearing Aids,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1169-1172, New Orleans, USA, May 2007.

  106. K.L. Chang, B.H. Gwee and Y.J. Zhang, “An Asynchronous Dual-Rail Multiplier Based on Energy-Efficient STFB Templates,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3267 - 3270, New Orleans, USA, May 2007.

  107. K. Mukherjee and B.H. Gwee, “A 32-Point FFT Based Noise Reduction Algorithm for Single Channel Speech Signals,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3928 - 3931, New Orleans, USA, May 2007.

  108. Chong-Fatt Law, Bah-Hwee Gwee, and Joseph S. Chang, “Optimized algorithm for computing invariants of ordinary Petri nets,” International Conference on Computer and Information Science, pp. 23-28, Hawaii, USA, July 2006.

  109. V. Adrian, B.H. Gwee and J.S. Chang, “An Acoustic Noise Suppression System with Musical Artifacts Reduction,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2529-2532, Island of Kos, Greece, May 2006.

  110. K.L. Chang and B.H. Gwee, “A Low-Energy Low-Voltage Asynchronous 8051 Microcontroller Core,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3181-3184, Island of Kos, Greece, May 2006.

  111. K.S. Chong, B.H. Gwee and J.S. Chang, “A Low-Energy Asynchronous FFT/IFFT Processor for Hearing Aid Applications,” IEEE Conference on Electronic Devices and Solid State Circuits, Hong Kong, pp. 751-754, Dec 2005.

  112. J.S. Chang, B.H. Gwee, L. Wanhammer, K. Palmkvist, T. Saramäki, O. Vanio, S. Phrakonkham, B. Soysouvanh, V. Chounramany and S. Saynasine, “An International Collaboration for the Development of an Online Postgraduate Course on Digital Circuit Technology,” 11th International Conference on Technology Supported Learning & Training (Online Educa Berlin), Berlin, Germany, Dec 2005.

  113. V. Adrian, B.H. Gwee and J.S. Chang, “A Combined Interpolatorless Interpolation and High Accuracy Sampling Process for Digital Class D Amplifiers,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 5405-5408, Kobe, Japan, May 2005.

  114. K.S. Chong, B.H. Gwee and J.S. Chang, “Low-Voltage Micropower Multipliers with Reduced Spurious Switching,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4078-4081, Kobe, Japan, May 2005.

  115. K.S. Chong, B.H. Gwee and J.S. Chang, “A robust low voltage low energy asynchronous carry-completion sensing adder for biomedical applications,” IEEE International Workshop on Biomedical Circuits and Systems (BioCAS), pp. 18-21, Singapore, Dec 2004.

  116. K.S. Chong, B.H. Gwee and J.S. Chang, “A Low-Voltage Low Power Accumulator,” International Symposium on Integrated Circuits, Devices and Systems (ISIC), Singapore, 2004.

  117. K.S. Chong, B.H. Gwee and J.S. Chang, “A Low Power 16-Bit Booth Leapfrog Array Multiplier Using Dynamic Adders,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. 2, pp. 437-440, Vancouver, Canada, May 2004.

  118. V. Adrian, B.H. Gwee and J.S. Chang, “A Novel Combined First and Second Order Lagrange Interpolation Sampling Process for a Digital Class D Amplifier,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. 3, pp. 233-236, Vancouver, Canada, May 2004.

  119. K.S. Chong, B.H. Gwee and J.S. Chang, “A Critical-Bank Filter Bank based on IFIR and Frequency Response Masking Techniques for Digital Hearing Instruments,” IEEE International Symposium on Consumer Electronics (ISCE), Sydney, Australia, 2003.

  120. B.H. Gwee and J.S. Chang, “A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems,” Third International Conference on Hybrid Intelligent Systems (HIS), Melbourne, Australia, 2003.

  121. K.H. Chang, B.H. Gwee and J.S. Chang, “A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File,” International Conference on VLSI, pp. 166-172, Las Vegas, USA, 2003.

  122. B.H. Gwee, J.S. Chang, V. Adrian and H. Amir, “A Novel Sampling Process and Pulse Generator for a Low Distortion Digital Pulse-Width Modulator for Digital Class D Amplifiers,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. IV, pp. 504-507, Bangkok, Thailand, May 2003.

  123. C.C. Chua, B.H. Gwee and J.S. Chang, “A Low-Voltage Micropower Asynchronous Multiplier for a Multiplierless FIR Filter,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. V, pp. 381-384, Bangkok, Thailand, May 2003.

  124. K.S. Chong, B.H. Gwee and J.S. Chang, “Low-Voltage Asynchronous Multiplier for Hearing Instruments,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 865-868, Arizona, USA, May 2002.

  125. K.S. Chong, B.H. Gwee and J.S. Chang, “Low-Voltage Asynchronous Adders for Low Power and High Speed Applications,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. 1, pp. 873-876, Arizona, USA, May 2002.

  126. H.Y. Li, B.H. Gwee and J.S. Chang, “A Digital Class D Amplifier Design Embodying a Novel Sampling Process and Pulse Generator,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. IV, pp. 826-829, Sydney, Australia, May 2001.

  127. J.S. Chang, B.H. Gwee, Y.S. Lon and M.T. Tan, “A Novel Low-Power Low-Voltage Class D Amplifier with Feedback for Improving THD, Power Efficiency and Gain Linearity,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. I, pp. 635-638, Sydney, Australia, May 2001.

  128. H.Y Li., B.H. Gwee, J.S. Chang and M.T. Tan, “A Novel Pulse-Width Modulation Sampling Process for Low-Power, Low-Distortion Digital Class D Amplifiers,” IEEE Midwest Symposium on Circuits and Systems (MWSCAS), vol. 1, pp. 514-517, Michigan, USA, Aug 2000.

  129. M.T. Tan, H.C. Chua, B.H. Gwee and J.S. Chang, “An Investigation on the Parameters Affecting Total Harmonic Distortion in Class D Amplifiers,” IEEE International Symposium on Circuits and Systems (ISCAS), vol. IV, pp. 193-196, Geneva, Switzerland, May 2000.

  130. B.H. Gwee and M.H. Lim, “A GA with Heuristic Based Decoder for Floorplanning with Flexible IC Modules,” International Symposium on Integrated Circuits, Devices and Systems (ISIC), Singapore, pp. 451-454, 1999.

  131. B.H. Gwee, M.H. Lim and B.H. Soong, “Self-Adjusting Diagnostic System for the Manufacture of Crystal Resonators,” IEEE Industry Application Society Annual Meeting (IAS), Toronto, Canada, vol. 3, pp. 2014-2020, Oct 1993.

  132. B.H. Gwee, M.H. Lim and J.S. Ho, “Solving Four-Colouring Map Problems using Genetic Algorithm,” International Two-Stream Conference on Artificial Neural Networks and Expert Systems (ANNES), pp. 322-323, 1993.

  133. B.H. Gwee and M.H. Lim, “Genetic Algorithm for the VLSI Floorplan Design Problem,” International Symposium on IC Design, Manufacture and Applications (ISIC), Singapore, pp. 475-479, 1993.

  134. M.H. Lim and B.H. Gwee, “Genetic Algorithms for Solving N-queens Problem,” International Joint Conference on Neural Networks (IJCNN), Beijing, China, 1992.

  135. M.H. Lim, B.H. Gwee and T.H. Goh, “Cause Associator Network for Fuzzily Deduced Conclusion in Process Control,” IEEE International Joint Conference on Neural Networks (IJCNN), pp. 1248-1253, Nov 1991.

  136. B.H. Gwee and M.H. Lim, “Condition Monitoring of Frequency Trimming Process,” International Symposium on IC Design, Manufacture and Applications (ISIC), pp. 220-226, 1991.