Grants

External Grants

Role Year Project Title Amount (S$) Source of Grant
PI 2024 - 2026 QUASAR - CREATE Thrust 1 814,000 NRF
PI 2024 - 2026 DeSCEmT – Project D 784,100 NRF
PI 2024 - 2026 Project Ravio 447,500 DSO
PI 2023 - 2028 Project HASTE 2,783,000 DSO
PI 2023 - 2024 Security Risk Evaluation for Logic Locking00 335,400 CSA
PI 2022 - 2025 Hardware Security Thrust (ii): Investigation and development of methods for analysing and evaluating hardware security mechanisms 704,000 DSTA
PI 2022 - 2025 Sub-project 3 - Exercisable Funding - Community Engagement 150,000 CSA
PI 2020 - 2024 Adaptive Machine Learning for Manufactured IC Image Analysis (AMELIA) 339,978 DSO
PI 2019 - 2024 Cyber-Hardware Forensics & Assurance Evaluation R&D Programme - Thrust (ii): Computer Aided Data Analysis of Recovered Data 642,000 NRF
PI 2019 - 2024 Assuring Hardware Security by Design in Systems on Chip 1,367,280 NRF
PI 2019 - 2020 SecuritasX 1,400 NUS LLP
PI 2017 - 2022 Hardware Assurance Phase II 2,060,000 DSO
Co-PI 2018 - 2019 GAP (PoC) Fund 124,975 (249,950) NRF
PI 2015 - 2017 Secured Memories and Anti-tamper Mechanism 300,000 DSO
PI 2014 - 2017 Secured Asynchronous-Logic Network-on-Chip Architecture 829,680 A*STAR PSF
PI 2013 - 2017 Hardware Assurance Phase II 1,384,000 DSO
PI 2009 - 2013 ASIC Failure Analysis - Development of a Hierarchy Extractor 1,170,000 DSO
PI 2009 - 2012 Fundamental Research: Ultra-Low Power Sub-Threshold Digital Circuits and Systems 1,323,145 MOE AcRF Tier 2
Co-PI 2010 - 2012 RFCMOS ASICs for Comm System and High Speed MUXDAC 300,000 (999,660) DSO
Co-PI 2009 - 2010 Digital Asynchronous-Logic: Dynamic Voltage Control 217,840 (435,680) USA DARPA
PI 2008 - 2009 A Hierarchy Extractor 200,000 DSO
PI 2006 - 2008 Low Power Asynchronous Design 200,000 DSO
Co-PI 2005 - 2007 Digital Amplifiers 500,000 (1,022,784) NTU - Panasonic Semiconductors
Co-PI 2005 - 2007 Low Power Asynchronous Digital Signal Processor IC Design 330,000 (661,908) NTU - Linköping University
PI 2003 - 2005 Collaborative Synchronous and Asynchronous Circuit Design 420,000 EU-AUNP
PI 2002 - 2006 Digital Multiplier with Reduced Spurious Switching 30,000 Ministry of Law Patent Application Fund

Internal Grants

Role Year Project Title Amount (S$) Source of Grant
PI 2024 - 2025 Camouflage IC 98,600 TL Seed Grant
PI 2021 - 2024 Event-driven Spiking Neural Networks Using Asynchronous-Logic Network-on-chip Routers in Field Programmable Gate Array (FPGA) 98,000 MOE AcRF Tier 1
PI 2006 - 2009 Development of Asynchronous-Logic EDA Tools and a High Performance Asynchronous Digital Signal Processor 47,586 MOE AcRF Tier 1
PI 2006 - 2009 Digital Amplifier 100,000 MOE RGM
PI 2006 - 2007 Signal Processing and Enablers based on Asynchronous Digital Logic 50,000 NTU ICT Grant
PI 2004 - 2007 Synchronous & Asynchronous Circuit Design 105,000 MOE AcRF Tier 1
PI 2003 - 2006 Development of Electrical, Electronic and Information System 140,000 MOE RGM
PI 2000 - 2004 Micropower Low Voltage Asynchronous Logic DSPs 78,552 MOE AcRF Tier 1

Note: For Co-PI grants, or where grants are from larger block grants to NTU, both the share of the grant and the total grant amount are indicated, e.g., “300,000 (600,000)”.