Bibliography

Dr Bah-Hwee Gwee received his BEng (Hons) degree from University of Aberdeen, UK, in 1990. He received his MEng and PhD degrees from Nanyang Technological University (NTU), Singapore, in 1992 and 1998 respectively. He was an Assistant Professor in School of EEE, NTU from 1999 to 2005 and has been an Associate Professor since 2005. He had held several school administrative committee appointments including Chairman of EEE Career Guidance Committee from 2000 - 2005, Chairman of EEE Outreach Committee from 2005 - 2009, Assistant Chair (Students) EEE from 2010 - 2014 and has been the Assistant Chair (Outreach) EEE since 2017. He is the Deputy-Director of National Integrated Centre for Evaluation (NiCE). Dr Gwee was the Principal Investigators (PIs) of a number of research projects including the ASEAN-European Union University Network Programme, Ministry of Education (MoE) Tier-1 and Tier-2, Defence Science Organisation, Defence Science and Technology Agency, Temasek Laboratories@NTU, A-STAR PSF, Cybersecurity Agency, National Research Foundation projects. He was also the co-PIs of DARPA (USA), NRF (SOCure), NRF (CHFA), NTU-Panasonic, NTU-Lingköping and GAP (Proof of Concept) Fund research projects. His total research grant is amounting to more than US$15m. He has filed 8 US patents in circuit design and hardware security, 5 of them have been granted by US PTO. His research interests include hardware security, hardware assurance, asynchronous circuit, machine learning and image processing. Dr Gwee was awarded Defence Technology Prize Team (R&D) category in 2016, TL@NTU Scientific Award, 2016, TL@NTU Best Publication Award in 2012 and the NTU EEE Teaching Excellence Award – Year 3 in 2013. He has co-founded 2 start-ups. Dr Gwee was the Chairman of IEEE Singapore Circuits and Systems Chapter in 2005, 2006, 2013 and 2016. He has been the members of IEEE Circuits and Systems Society (CASS) DSP, VSA and Bio-CAS Technical Committees (TC) since 2004. He was the Chairman of IEEE CASS DSP TC from 2018 - 2020. He has served in the Organizing Committees for IEEE BioCAS-2004, IEEE APCCAS-2006, Technical Program Chair for ISIC-2007, ISIC-2011, ISIC-2016 and served in the steering committee for IEEE APCCAS 2006 - 2008. He was the General Chair of IEEE DSP 2018, IEEE SOCC 2019, IEEE ISICAS 2021 and will be the General Chair of ISCAS 2024 (IEEE CAS Society flagship conference). He was the Associate Editor for IEEE CAS Magazine (from 2020 – present), , IEEE Transactions on Circuits and Systems I – Regular Papers (T-CAS I) from 2012-2013 and IEEE Transactions on Circuits and Systems II – Express Brief (T-CAS II) from 2010 - 2011, from 2018 – 2019 and from 2020 – 2021. He serves in the editorial board of IEEE Circuits and Systems Magazine from 2021 – 2022 and Journal of Circuits, Systems and Signal Processing (CSSP) from 2007 - 2012. He was an IEEE Distinguished Lecturer for CAS Society from 2009 – 2010 and from 2017 - 2018. He was the keynote speaker of IEEE MCSoC 2021, IEEE PAINE 2020 and IEEE APCCAS 2020.

Keynote Speeches / Awards

• Keynote Speech, International Workshop on Advanced Cyber-security and Low Power Design for IoT Systems, Vietnam, 2023.
• Keynote speaker in IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE) in Washington, DC, USA, 2020.
• Keynote speaker in IEEE International Symposium on Embedded Multicore / Many-core Systems-on-Chip (MCSoC) in Singapore, 2021.
• Keynote speaker in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) in Vietnam, 2020.
• Invited Speaker, International Symposium of Circuits and Systems - Young Professional Program, (ISCAS) in Daegu, South Korea, 25 May 2021.
• Tutorial Organizer/Speaker - IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Kunming, China, 2020.
• Distinguished Lecturer IEEE CASS DL in Hardware Assurance, 2017 – 2018
• Defence Technology Prize (R&D) for outstanding technological contribution to Hardware Assurance by Singapore Government, 2016.
• TL@NTU Scientific Award - Temasek Laboratories @ Nanyang Technological University, 2016
• Teaching Excellence Award Year 3 - EEE, Nanyang Technological University, 2013
• Best Publication Award - Temasek Laboratories @ Nanyang Technological University, 2012.
• Best Student Paper Award, IEEE Sub-threshold Microelectronics Conference, USA, 2012
• IEEE CASS DL in Asynchronous Circuit Design, 2009 – 2010

Experience

Education

• Ph.D., School of Electrical and Electronic Engineering, Nanyang Technological University (1998)
• M.Eng., School of Electrical and Electronic Engineering, Nanyang Technological University (1992)
• B.Eng. (First Class Honours), University of Aberdeen, U.K. (1990)

Work Experience

• Associate Professor, School of EEE, Nanyang Technological University (NTU) (2005 - now)
• Deputy Director, National Integrated Centre for Evaluation (2021 - now)
• Research Director, Centre of Hardware Assurance – Circuit Analysis, Temasek Laboratories@NTU) (2019 – now)
• Assistant Chair (Outreach), School of EEE, NTU (2017 – now)
• Member, NTU Teaching Council, NTU (2014 – now)
• Assistant Chair (Students), School of EEE, NTU (2008 – 2014)
• Assistant Professor, School of EEE, NTU (1999 – 2005)

Editorial Board Activities

• Editorial Board Member of IEEE Circuits and Systems Magazine from 2021 - present
• Associate Editor, IEEE Transactions on Circuits and Systems II - Express Briefs, USA (2018 – now)
• Associate Editor, IEEE Transactions on Circuits and Systems I – Regular Papers, USA (2012 – 2013)
• Associate Editor, IEEE Transactions on Circuits and Systems II - Express Briefs, USA (2010 – 2012)
• Associate Editor, Journal of Circuits, Systems and Signal Processing, USA (2007 – 2012)
• Guest Editor, Guest Editor of Special issue in IEEE Transactions on Circuits and Systems II on ISICAS (2018)

Technical and Standard Committees

• IEEE Hardware Security Standard Committee (2022 - now)
• Chair, Digital Signal Processing (DSP) Technical Committee, IEEE Circuits and Systems Society (2018 - 2020)
• Secretary, Digital Signal Processing (DSP) Technical Committee, IEEE Circuits and Systems Society (2016 - 2018)
• Member, VLSI Systems and Applications (VSA) Technical Committee, IEEE Circuits and Systems Society (2005 - now)
• Member, Biomedical Circuits and Systems (Bio-CAS) Technical Committee, IEEE Circuits and Systems Society (2010 - now)
• Member, Life Science Systems and Applications (LiSSA) Technical Committee, IEEE Circuits and Systems Society (2005 - 2010)
• Deputy Chair, IEEE Circuits and Systems Chapter in Singapore (2017 - 2018)
• Chair, IEEE Circuits and Systems Chapter in Singapore (2016 - 2016)
• Chair, IEEE Circuits and Systems Chapter in Singapore (2013 - 2013)
• Deputy Chair, IEEE Circuits and Systems Chapter in Singapore (2010 - 2011)
• Treasurer, IEEE Circuits and Systems Chapter in Singapore (2008 - 2009)
• Deputy Chair, IEEE Circuits and Systems Chapter in Singapore (2007 - 2007)
• Chair, IEEE Circuits and Systems Chapter in Singapore (2005 - 2006)
• Deputy Chair, IEEE Circuits and Systems Chapter in Singapore (2000 - 2001)

Conference Organizing Committees

• General Chair, IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, 2024
• General Chair, IEEE Symposium on Integrated Circuits and Systems (ISICAS), Singapore, 2021.
• General Chair, IEEE Systems-on-Chip Conference (SOCC) , Singapore, 2019.
• General Chair, IEEE Digital Signal Processing (DSP), Shanghai, China, 2018.
• Track Chair, IEEE International Symposium on Circuits and Systems DSP Track, (ISCAS), 2016 – 2020.
• Technical Program Co-Chair, International Symposium of Integrated Circuits (ISIC), Singapore, 2016.
• Local Arrangement Co-Chair, IEEE Digital Signal Processing (DSP), Singapore, 2015.
• Publicity Co-Chair, Asia and South Pacific Design Automation Conference (ASP DAC), Singapore, 2014.
• Technical Program Committee, Asia and South Pacific Design Automation Conference (ASP DAC), Japan, 2013.
• Technical Program Committee, International Symposium on VLSI Design, Automation and Test (VLSI DAT), Taiwan, 2012 – 2013.
• Technical Program Chair, International Symposium of Integrated Circuits (ISIC), Singapore, 2011.
• Technical Program Committee, International Symposium on Communications and Information Technologies (ISCIT), 2010
• Technical Program Committee, Pacific Signal and Information Processing Association (APSIPA), 2010.
• Technical Program Committee, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2010.
• Technical Program Committee, IEEE Workshop on Biomedical Circuits and Systems (BioCAS), 2008 - 2010.
• Technical Program Chair, International Symposium of Integrated Circuits (ISIC), Singapore, 2007.
• Publication Chair, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore, 2006
• Steering Committee Member, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2005 - 2007.
• Local Arrangment Co-Chair, IEEE Workshop on Biomedical Circuits and Systems (BioCAS), Singapore, 2004.

Courses Taught

• NM6008 – Digital IC Design Lab for NTU-TUM MSc (IC Design)
• EE6309 - VLSI Systems
• EE4344 - Analysis and Design of Integrated Circuits
• EE3019 – Integrated Electronics
• IE2104 – Digital Electronics
• CET919 - Design for Trust
• CET921 - Side-Channel-Attacks & Countermeasures

Research

Research Interests

• Hardware Assurance
• Hardware Security
• Asynchronous Circuit
• Machine Learning

Research Projects

• Camouflage IC (Project PI, 2024 - 2024)
• Project HASTE (Project PI, 2023 - 2028)
• Security Risk Evaluation for Logic Locking (Project PI, 2023 - 2024)
• Cyber-Hardware Forensics & Assurance Evaluation R&D Programme (Project PI, 2019 – 2024)
• National Integrated Centre for Evaluation, (Project PI, 2019 – 2022)
• SOCure: Assuring Hardware Security by Design in Systems on Chip (Project PI, 2019 – 2024)
• Hardware Assurance Phase II (Project PI, 2017 – 2022)
• Side-Channel-Attack-Resistant (SCA-Resistant) Nano AES-128 Accelerator for Internet-Of-Thing (IoT) (Co-PI, 2018 – 2022)
• Secured Memories and Anti-tamper Mechanisms (PI, 2015 – 2019)
• Secured Asynchronous-Logic Network-on-Chip Architecture (PI, 2014 – 2017)
• Hardware Assurance (Project PI, 2013 – 2017)
• ASIC Failure Analysis - Development of a Hierarchy Extractor (Project PI, 2009 – 2013)
• Fundamental Research: Ultra-Low Power Sub-Threshold Digital Circuits and Systems (PI, 2009 – 2012)
• RFCMOS ASICs for Comm System and High Speed MUXDAC (Co-PI, 2010 -2012)
• Digital Asynchronous-Logic: Dynamic Voltage Control (DARPA Co-PI, 2009 -2010)
• A Hierarchy Extractor (PI, 2008 – 2009)
• Development of Asynchronous-Logic EDA Tools and a High Performance Asynchronous Digital Signal Processor (PI, 2006 – 2009)
• Digital Amplifier (PI, 2006 – 2009)
• Low Power Asynchronous Design (PI, 2006 – 2008)
• Signal Processing and Enablers based on Asynchronous Digital Logic (PI, 2006 – 2007)
• Low Power Asynchronous Digital Signal Processor IC Design, NTU- Linköping (Co-PI, 2005 – 2008)
• Digital Amplifiers, NTU-Panasonic (Co-PI, 2005 – 2007)
• Synchronous & Asynchronous Circuit Design (PI, 2004 – 2007)
• Collaborative Synchronous and Asynchronous Circuit Design, ASEAN-EU University Network Programme (AUNP) (PI, 2003 – 2005)
• Development of Electrical, Electronic and Information System (PI, 2003 – 2006)
• Digital Multiplier with Reduced Spurious Switching (PI, 2002 – 2006)
• Micropower Low Voltage Asynchronous Logic DSPs (PI, 2000 – 2004)

Technologies

• Dr. Gwee and his team had proposed a high speed and yet robust asynchronous quasi-delay-insensitive circuit - Sense-Amplifier Half-Buffer (SAHB) circuit technique with emphases on high operational robustness, high speed, and low power dissipation [Gwee TVLSI 2017]. The SAHB has been commercialized by a start-up company,Async2Secure.
• Dr. Gwee and his team had proposed a 16-channel non-uniform spaced critical band filter bank designed for hearing aid applications [Gwee TCAS-II] 2006], as human psychoacoustic hearing response is not linearly spaced. The technology has been employed by a well-established hearing aid company,Digital Hearing Aid Centre.

Publication

Journal Papers

• W.G. Ho, K.-S. Chong, T.H. Kim, and B.H. Gwee, “A Secure Data-Toggling SRAM for Confidential Data Protection,” IEEE Transactions on Circuits and Systems I: Regular Paper, v66, n11, pp. 4186-4199, Nov 2019.
• A. A. Pammu, K. S. Chong, Yi Wang and B. H. Gwee, "A Highly Efficient Side Channel Attack with Profiling through Relevance Learning on Physical Leakage Information," IEEE Transactions on Dependable Secure Computing, v16, n3, pp. 376-387, May/Jun 2019.
• A. A. Pammu, W.G. Ho, K. Z. L. Ne, K. S. Chong and B. H. Gwee, “A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor,” IEEE Transactions on Information Forensics & Security, v14, n4, pp. 1023-1036, Apr 2019.
• D. Cheng, Y. Shi, B.H. Gwee, T. Lin and K.A.Toh, “A Hierarchical Multi-Classifier System for Automated Analysis of Delayered IC Images,” IEEE Intelligent Systems, v39, n2, pp. 36-43, Mar/Apr 2019.
• D. Cheng, Y. Shi, T. Lin, B.H. Gwee and K.A.Toh, “Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images,” IEEE Transactions on Circuits and Systems II: Express Briefs, v65, n12, pp. 1849-1853, Dec 2018.
• W.G. Ho, K.-S. Chong, K.Z.L. Ne, and B.H. Gwee, “Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design,” IEEE Transactions on Very Large Scale Integration Systems, v26, n1, pp. 196-200, Jan 2018.
• C. Keer, V. Adrian, B.H. Gwee and J.S. Chang, “A Noise-Shaped Randomized Modulation for Switched-Mode DC-DC Converters,” IEEE Transactions on Circuits and Systems I: Regular Paper, v65, n1, pp. 394-405, Jan 2018.
• A. A. Pammu, K.-S. Chong and B.-H. Gwee, “A Highly-Secured Arithmetic Hiding cum Look-Up Table (AHLUT) based S-Box for AES-128 Implementation,” Advances in Science, Technology and Engineering Systems Journal, Special issue on Recent Advances in Engineering Systems, v2, n3, pp. 420-426, 2017.
• K.S. Chong, W.G. Ho, T. Lin, B.H. Gwee, and J.S. Chang, “Sense-Amplifier Half-Buffer (SAHB): A Low Power High-Performance Asynchronous-Logic QDI Cell Template,” IEEE Transactions on Very Large Scale Integration Systems, (Regular Paper), v25, n2, pp. 402-415, Feb 2017.
• W.G. Ho, K.S. Chong, B.H. Gwee, and J.S. Chang, “Low Power Sub-Threshold Asynchronous QDI 32-Bit ALU based on Autonomous Signal-Validity Half-Buffer (ASVHB),” IET Circuits, Devices and Systems, v9, n4, pp. 309-318, Jul 2015.
• R. Zhou, K.S. Chong, B.H. Gwee and J.S. Chang, “A Low Overhead Quasi-Delay-Insensitive (QDI) Asynchronous Data Path Synthesis Based on Microcell-Interleaving Genetic Algorithm (MIGA),” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Regular Paper), v33, n7, pp. 989-1002, Jul 2014.
• J. Chen, K.S. Chong, B.H. Gwee, “Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing,” Journal of Circuits, Systems and Signal Processing, v33, n4, pp. 1-13, Apr 2014.
• K.L. Chang, J.S. Chang, B.H. Gwee, K.S. Chong, “Synchronous-logic and Asynchronous-logic 8051 Microcontroller Cores for Powering the Internet of Things: A Comparative Study on Dynamic Voltage Scaling and Variation Effects,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems - Special Issue on Low-Power, Reliable, and Secure Solutions for Realization of Internet of Things, v3, n1, pp. 23-34, Mar 2013.
• T. Lin, K.S. Chong, J.S. Chang and B.H. Gwee “An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive VDD System for Wireless Sensor Networks,” IEEE Journal of Solid State Circuits, (Regular Paper), v48, n2, pp. 573-586, Feb 2013.
• K.S. Chong, K.L. Chang, B.H. Gwee and J.S. Chang, “Synchronous-logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors,” IEEE Journal of Solid State Circuits, (Regular Paper), v47, n3, pp. 769-780, Mar 2012.
• C.F. Law, B.H. Gwee and J.S. Chang, “Modeling and Synthesis of Asynchronous Pipelines,” IEEE Transactions on Very Large Scale Integration Systems, (Regular Paper), v19, n4, pp.682-695, April 2011.
• Y. Shi, B.H Gwee and J. Chang, “Asynchronous DSP for Low-power Energy-efficient Embedded Systems,” Microprocessors and Microsystems, v35, n1, pp. 318–328, 13 Feb 2011.
• V. Adrian, J.S. Chang and B.H. Gwee, “A Randomized Wrapped-Around Pulse Position Modulation Scheme for DC-DC Converters,” IEEE Transactions on Circuits and Systems I: Regular Paper, v59, n9, pp. 2320 – 2333, Sep 2010.
• B.H. Gwee, J.S. Chang, Y. Shi, C.C. Chua and K.S. Chong, “A Low-Voltage Micropower Asynchronous Multiplier with Shift-Add Multiplication Approach,” IEEE Transactions on Circuits and Systems I: Regular Paper, v56, n7, pp. 1349-1359, July 2009.
• V. Adrian, J.S. Chang and B.H. Gwee, “A Low Voltage Micropower Digital Class D Amplifier Modulator for Hearing Aids,” IEEE Transactions on Circuits and Systems I: Regular Paper, v56, n2, pp. 337-349, Feb 2009.
• B.H. Gwee and J.S. Chang, “An Efficient Hybrid Genetic Hill-climbing Algorithm for Solving n-region 4-coloring Map Problems,” Far East Journal of Experimental and Theoretical Artificial Intelligence - Special Issue on Hybrid Intelligent Systems, v1, n2, pp.151-178, 2008.
• C.F. Law, B.H. Gwee and J.S. Chang, “Asynchronous Control Network Optimization Using Fast Minimum Cycle Time Analysis,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (Regular Paper), v27, n6, pp. 985-998, Jun 2008.
• K.S. Chong, B.H. Gwee and J.S. Chang, “Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors,” IEEE Journal of Solid State Circuits, (Regular Paper), v42, n9, pp. 2034-2045, Sep 2007.
• C.F. Law, B.H. Gwee and J.S. Chang, “Fast and memory-efficient Invariant Computation of Ordinary Petri Nets,” IET Proceedings on Computers & Digital Techniques, vol. 1, no. 5, pp. 612-624, Sep 2007.
• K.S. Chong, B.H. Gwee, and J.S. Chang, “Design of Several Asynchronous-Logic Macrocells for a Low-Voltage Micropower Cell Library,” IET Proceedings on Circuits, Devices and Systems, vol. 1, no. 2, pp. 161-169, Apr 2007.
• K.S. Chong, B.H. Gwee, and J.S. Chang, “Low Energy 16-bit Booth Leapfrog Array Multiplier using Dynamic Adders,” IET Proceedings on Circuits, Devices and Systems, vol. 1, no. 2, pp. 170-174, Apr 2007.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A 16-Channel Low Power Non-Uniform Spaced Filter Bank Core for Digital Hearing Aids,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 9, pp. 853-857, 2006.
• B.H. Gwee, J.S. Chang and V. Adrian, “A Micropower Low Distortion Digital Class D Amplifier based on an Algorithmic Pulse Width Modulator,” IEEE Transactions on Circuits and Systems I: Regular Paper, vol.52, no. 10, pp. 2007-2022, Oct 2005.
• B.H. Gwee and M.H. Lim, “An Evolution Search Algorithm for Solving N-queen Problems,” International Journal of Computer Applications in Technology (Regular Paper), vol. 24, No. 1, pp. 43-48, Jun 2005.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A Micropower Low-Voltage Low Power Multiplier with Reduced Spurious Switching,” IEEE Transactions on Very Large Scale Integration Systems, (Regular Paper), vol. 13, no. 2, pp. 255-265, Feb 2005.
• M.T. Tan, J.S. Chang, H.C. Chua and B.H. Gwee, “An Investigation into the Parameters Affecting THD in Low-voltage Low-Power Class D Amplifier,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, (Regular Paper), vol. 50, no. 10, pp. 1304-1315, Oct 2003
• Gwee B.H. and Chang J.S., “A Novel Delta-Compensation Sampling Process for Digital Class D Amplifiers,” Electrical and Electronic Engineering Research, pp. 24-25, 2003.
• B.H. Gwee, J.S. Chang and H.Y. Li, “A Micropower Low-Distortion Digital Pulsewidth Modulator for a Digital Class D Amplifier,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing (Regular Paper), vol. 49, no. 4, pp. 245-256, Apr 2002.
• Gwee B.H. and Lim M.H., “Flexible IC Floorplan Design with Genetic Algorithm,” Electrical and Electronic Engineering Research, pp. 22-23, 2000.
• B.H. Gwee and M.H. Lim, “A GA with Heuristic Based Decoder for IC Floorplanning,” Integration, the VLSI Journal, vol. 28, no.2, pp. 157-172, 1999
• B.H. Gwee, M.H. Lim and B.H. Soong, “Self-adjusting Diagnostic System for the Manufacture of Crystal Resonators,” IEEE Transactions on Industry Applications, (Regular paper), vol. 32, no. 1, pp. 73-79, Jan/Feb 1996.
• B.H. Gwee and M.H. Lim, “Polyominoes Tiling by a Genetic Algorithm,” Computational Optimization and Applications, vol. 6, pp. 273-291, Nov 1996.
• M.H. Lim, S. Rahardja and B.H. Gwee, “A GA Paradigm for Learning Fuzzy Rules,” Fuzzy Sets and Systems, vol. 82, pp. 177-186, Sep 1996.
• M.H. Lim, B.H. Gwee and Y. Kawada, “Intelligent Monitoring of Frequency Trimming Process,” Journal of Intelligent Manufacturing, vol. 4, pp. 375-383, 1993.

Patent

• K.S. Chong, B.H. Gwee, W.G. Ho and N.K.Z. Lwin, “Camouflage Digital Cells To Prevent Reverse Engineering,” PCT US Patent Applications and Singapore provisional Patent Application No. 10201803673Y, 2 May 2018.
• K.S. Chong, B.H. Gwee and A. A. Pammu, “Hardware Security to Countermeasure Side-Channel Attacks,” PCT US Patent Applications and Singapore Patent Application No. 10201702226R, 19 Mar 2018.
• J.S. Chang, B.H. Gwee and K.S. Chong, “Digital Cell,” US Patent No. US 8,994,406 B2, File on, 19 Dec 2012, Granted on 31 Mar 2015.
• J.S. Chang, B.H. Gwee and K.S. Chong, “Asynchronous-Logic for Full Dynamic Voltage Scaling,” US Patent No. US 8,791,717 B2, File on, 14 Jul 2011, Granted on 29 Jul 2014.
• J.S. Chang, B.H. Gwee and K.S. Chong, “Dual-Rail Asynchronous-Logic Quasi-Delay-Insensitive (QDI) Pre-Charged Static Digital Circuits,” US Provisional Patent Application, 19 Jan 2012.
• J.S. Chang, B.H. Gwee and K.S. Chong, “Sense-Amplifier Quasi-Delay-Insensitive (SAQDI) Asynchronous-Logic,” US Provisional Patent Application No. 61/577,367, 19 Dec 2011.
• J.S. Chang, B.H. Gwee and K.S. Chong, “A Digital Multiplier with Reduced Spurious Switching by Means of Latch Adders,” US Patent No. US 7,206,801, Filed on 14 May 2003, Granted on 17 April 2007
• J.S. Chang, B.H. Gwee and K.S. Chong, “A Digital Multiplier with Reduced Spurious Switching by Means of Latch Adders,” Singapore Patent Application No. 200203073-2, Filed on 22 May 2002, Granted on 28 April 2006.
• J.S. Chang, B.H. Gwee and C.F. Law, “A Compiler for Elaborating Hardware Description Language Specifications of Asynchronous Digital-Logic Systems,” Singapore Patent Application No. E05/00203791, Filed on 28-Nov-2005.

Monograph

• H. Li and B.H. Gwee, Digital Pulse Width Modulator, ISBN 978-3-639-17876-0, VDM Publishing House Ltd. 2009.

Book Chapter

• B.H. Gwee and K.S. Chong, “Low Power Asynchronous Circuit Design – An FFT/IFFT Processor,” in CMOS Nanoelectronics, kris iniewski (Ed.), 2010.
• B.H. Gwee and J.S. Chang, in Design and Application of Hybrid Intelligent Systems, A. Abraham, M. Köppen, K. Franke (Eds.), IOS Press, pp. 252-261, 2003.

Conference Paper

• J.S. Ng, W.G. Ho, K.S. Chong and B.H. Gwee, “A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES),” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2020, Seville, Spain, 17-20 May 2020.
• W.G. Ho, K.S. Chong, T.H. Kim and B.H. Gwee, “A Secure Data-Toggling SRAM for Confidential Data Protection,” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2020, Seville, Spain, 17-20 May 2020.
• W.G. Ho, N.K.Z. Lwin, K.S. Chong and B.H. Gwee, “A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications,” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2020, Seville, Spain, 17-20 May 2020.
• K.S. Chong, A. Shreedhar, K.Z.L. Ne, A.K. Nay, W.G. Ho, C. Wang, J. Zhou, B.H. Gwee and J. Change, “Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells,” Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2019), Xi’an, China, 16-17 Dec 2019.
• W.G. Ho, A. A. Pammu, N.K.Z. Lwin, K.S. Chong and B.H. Gwee, “Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications,” 32nd IEEE International Systems-On-Chip Conference, IEEE SOCC 2019, Singapore, 4-6 Sep 2019.
• D. Cheng, Y. Shi, T. Lin, B.H. Gwee and K.A.Toh, “Global Template Projection and Matching Method for Training-free Analysis of Delayered IC Images,” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2019, Sapporo, Japan, 26-29 May 2019.
• A.R. Shreedhar, K.S. Chong, N.K.Z. Lwin, N.A. Kyaw, L. Nalangilli, W. Shu, J.S. Chang and B.H. Gwee, “Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard (AES) Design,” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2019, Sapporo, Japan, 26-29 May 2019.
• X. Hong, D. Cheng, Y. Shi, T. Lin and B.H. Gwee, “Deep Learning for Automatic IC Image Analysis,” Proceedings of IEEE 23rd International Conference on Digital Signal Processing, IEEE DSP 2018, Shanghai, China, 19-21 Nov 2018.
• W.G. Ho, Z. Zheng, K.S. Chong and B.H. Gwee, “A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation,” Proceedings of IEEE 23rd International Conference on Digital Signal Processing, IEEE DSP 2018, Shanghai, China, 19-21 Nov 2018.
• D. Cheng, Y. Shi, T. Lin, B.H. Gwee and K.A.Toh, “Hybrid K-Means Clustering and Support Vector Machine Method for via and Metal Line Detections in Delayered IC Images,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2018, Florence, Italy 27-30 May 2018
• W.G. Ho, K.S. Chong, K. Z. L. Ne, B.H. Gwee and J.S. Chang, “Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2018, Florence, Italy 27-30 May 2018.
• C. Keer, V. Adrian, B.H. Gwee and J.S. Chang, “A Low-Harmonics Low-Noise Randomized Modulation Scheme for Multi-Phase DC-DC Converters,” Proceedings of 2017 IEEE International NEWCAS Conference, IEEE NEWCAS’2017, Strasbourg, France, 25-28 June 2017.
• W.G. Ho, K.S. Chong, B.H. Gwee and J.S. Chang, “Low-Power High Speed Robust Asynchronous-Logic QDI Sense Amplifier Half-Buffer Circuits for Power Management Applications,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2017, Baltimore, Maryland, USA, 28-31 May 2017
• A. A. Pammu, K.-S. Chong and B.-H. Gwee, “Highly Secured State-shift Local Clock Circuit to Countermeasure against Side Channel Attack,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2017, Baltimore, Maryland, USA, 28-31 May 2017.
• Q. Liu, V. Adrian, B.H. Gwee and J.S. Chang, “A Class-E RF Power Amplifier with a Novel Matching Network for High-Efficiency Dynamic Load Modulation,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2017, Baltimore, Maryland, USA, 28-31 May 2017.
• J. Lim, W.G. Ho, K.S. Chong, B.H. Gwee and J.S. Chang, “DPA-Resistant QDI Dual-Rail AES S-Box Based on Power-Balanced Weak-Conditioned Half-Buffer,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2017, Baltimore, Maryland, USA, 28-31 May 2017
• A. A. Pammu, K.-S. Chong and B.-H. Gwee, “Highly Secured Arithmetic Hiding based S-Box on AES-128 Implementation,” Proceedings of International Symposium on Integrated Circuits, ISIC’2016, (Best Student Paper Award), Singapore, 12-14 Dec 2016
• Q. Liu, V. Adrian, B.H Gwee and J.S. Chang, “A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled output matching network,” Proceedings of International Symposium on Integrated Circuits, ISIC’2016, Singapore, 12-14 Dec 2016.
• A. A. Pammu, K.-S. Chong, K. Z. L. Ne, W.-G. Ho, N. Liu and B.-H. Gwee, “Success Rate Model for Fully AES-128 in Correlation Power Analysis,” Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, Oct. 2016
• A. A. Pammu, K.-S. Chong, W.-G. Ho and B.-H. Gwee, “Interceptive Side Channel Attack on AES-128 Wireless Communications for IoT Applications,” Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Korea, Oct. 2016.
• A. A. Pammu, K.S. Chong and B.H. Gwee, “Secured Low Power Overhead Compensator Look-Up-Table (LUT) Substitution Box (S-Box) Architecture,” Proceedings of IEEE International Conference on Networking, Architecture, and Storage, IEEE NAS’2016, (Best Presentation Award), California, USA, 8-10 Aug 2016.
• W.G. Ho, N. Liu, K.Z.L. Ne, K.S. Chong, B.H. Gwee and J.S. Chang, “High Performance Low Overhead Template-Based Cell-Interleave Pipeline (TCIP) for Asynchronous-Logic QDI Circuits,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2016, Montreal, Canada, 22-25 May 2016.
• W.G. Ho, K.Z.L. Ne, N.P. Srinivas, K.S. Chong, T.H. Kim and B.H. Gwee, “Area-Efficient and Low Stand-by Power 1K-Byte Transmission-Gate-Based Non-Imprinting High-Speed Erase (TNIHE) SRAM,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2016, Montreal, Canada, 22-25 May 2016.
• N. Liu, K.S. Chong, W.G. Ho, B.H. Gwee and J.S. Chang, “Low Normalized Energy Derivation Asynchronous Circuit Synthesis Flow through Fork-Join Slack Matching for Cryptographic Applications,” Proceedings of Design, Automation and Test in Europe, DATE’2016, 14-18 Mar 2016.
• K.S. Chong, K.Z.L. Ne, W.G. Ho, N. Liu, A. Akbar, B.H. Gwee and J.S. Chang, “Counteracting Differential Power Analysis: Hiding Encrypted Data from Circuit Cells,” Proceedings of IEEE Conference on Electron Devices and Solid-State Circuits, IEEE EDSSC’2015, (Invited Paper), Singapore, 1-4 Jun 2015.
• H. Yin, B.H. Gwee, Z. Lin, A. Kumar, S.G. Razul and C.M.S. See, “Novel Real-Time System Design for Floating-point Sub-Nyquist Multi-Coset Signal Blind Reconstruction,” IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2015, pp. 954-957, Lisbon, Portugal, 24-27 May 2015.
• W.G. Ho, K.S. Chong, B.H. Gwee, and J.S. Chang, “High Robustness Energy- and Area-Efficient Dynamic-Voltage-Scaling 4-phase 4-rail Asynchronous-Logic Network-on-Chip (ANoC),” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2015, pp. 1913-1916, Lisbon, Portugal, 24-27 May 2015.
• R. Zhou, K.S. Chong, T. Lin, B.H. Gwee, and J.S. Chang, “A Single-VDD Half-Clock-Tolerant Fine-Grained Dynamic Voltage Scaling Pipeline,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2015, pp. 2589-2592, Lisbon, Portugal, 24-27 May 2015.
• W.G. Ho, K.S. Chong, B.H. Gwee, J.S. Chang and K.Z.L. Ne, “A Dynamic-Voltage-Scaling 1kbyte×8-bit Non-Imprinting Master-Slave SRAM with High Speed Erase for Low-Power Operation,” Proceedings of International Symposium on Integrated Circuits, ISIC’2014, pp. 320-323, Singapore, 10-12 Dec 2014.
• T.S. Ng, Y. Sun, V. Adrian, B.H Gwee, and J.S. Chang, “Design of an Output Stage for High Switching Frequency DC-DC Converters,” Proceedings of International Symposium on Integrated Circuits, ISIC’2014, pp. 488-491, Singapore, 10-12 Dec 2014.
• S. Nashit, V. Adrian, K. Cui, Q.A. Mai, B.H. Gwee, and J.S. Chang, “A Self-Oscillating Class D Audio Amplifier with Dual Voltage and Current Feedback,” Proceedings of International Symposium on Integrated Circuits, ISIC’2014, pp. 480-483, Singapore, 10-12 Dec 2014.
• W.G. Ho, K.S. Chong, B.H. Gwee, and J.S. Chang, “Low Delay-Variation Sub-/Near-Threshold Asynchronous-to-Synchronous Interface Controller for GALS Network-on-Chips,” IEEE Asia Pacific Conference on Circuits and Systems, IEEE APCCAS’2014, pp. 5-8, Ishigaki, Japan, 17-20 Nov 2014.
• V. Adrian, C. Keer, B.H. Gwee and J.S. Chang, “A Randomized Modulation Scheme for Filterless Digital Class D Audio Amplifiers,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2014, pp. 774-777, Melbourne, Australia, 1-5 June 2014.
• R. Zhou, K.S. Chong, B.H. Gwee, J.S. Chang and W.G. Ho, “Synthesis of Asynchronous QDI Circuits using Synchronous Coding Specifications,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2014, pp. 153-156, Melbourne, Australia, 1-5 June 2014.
• Y. Shi and B.H. Gwee, “Designing Globally-Asynchronous-Locally-Synchronous System from Multi-Rate Simulink Model,” IEEE New Circuits and Systems Conference, Proceedings of IEEE NEWCAS’2013, pp. 1-4, Paris, France, 16-19 Jun 2013.
• W.G. Ho, K.S. Chong, B.H. Gwee and J.S. Chang, “Low Power Sub-Threshold Asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-Bit ALU,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2013, pp. 353-356, Beijing, China, 19-23 May 2013.
• K.L Chang, K.S. Chong, B.H. Gwee and J.S. Chang, “A Dual-Core 8051 Microcontroller System Based on Synchronous-Logic and Asynchronous-Logic,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2013, pp. 3022-3025, Beijing, China, 19-23 May 2013.
• T. Lin, K.S. Chong, J.S. Chang, and B.H. Gwee, “A Robust Asynchronous Approach for Realizing Ultra-Low Power Digital Self-Adaptive VDD Scaling System,” Proceedings of IEEE Subthreshold Microelectronics Conference, IEEE SubVt 2012, pp. 1-3, Waltham, Massachusetts, USA, (Best Student Paper Award), 9-10 Oct 2012.
• Y. Shi, B.H. Gwee, Y. Ren, T.K. Phone and C.W. Ting, “Extracting Functional Modules from Flattened Gate-Level Netlist,” Proceedings of International Symposium on Communications and Information Technologies (ISCIT’2012), pp. 538-543, Gold Coast, Australia, 2-5 Oct 2012.
• K.L Chang, K.S. Chong, B.H. Gwee and J.S. Chang, “A Comparative Study on Asynchronous Quasi-Delay-Insensitive Templates,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2012, pp. 1819-1822, Seoul, Korea, 20-23 May 2012.
• W.G. Ho, K.S. Chong, T. Lin, B.H. Gwee and J.S. Chang, “Energy-Delay Efficient Asynchronous-Logic 16x16-Bit Pipelined Multiplier Based on Sense Amplifier-Based Pass Transistor Logic,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2012, pp. 492-495, Seoul, Korea, 20-23 May 2012.
• J. Chen, K.S. Chong, B.H. Gwee and J.S. Chang, “An Ultra-Dynamic Voltage Scalable (U-DVS) 10T SRAM with bit-interleaving capability in 65 nm CMOS,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2012, pp. 1835-1838, Seoul, Korea, 20-23 May 2012.
• R. Zhou, K.S. Chong, B.H. Gwee, and J.S. Chang, “Quasi-Delay-Insensitive Compiler: Automatic Synthesis of Asynchronous Circuits from Verilog Specifications,” Proceedings of IEEE International Midwest Symposium on Circuits and Systems, IEEE MWSCAS’ 2011, pp. 1-4, Seoul, Korea, 7-10 Aug 2011.
• W.G. Ho, K.S. Chong, B.H. Gwee, J. Chang and M.F. Yee, “A power-efficient integrated input/output completion detection circuit for asynchronous-logic quasi-delay-insensitive Pre-Charged Half-Buffer,” Proceedings of International Symposium on Integrated Circuits, ISIC’2011, pp. 376 - 379, Singapore, 12-14 Dec 2011.
• J. Chen, K.S. Chong, B.H. Gwee and J.S. Chang, “A Low-Power Dual-Rail Inputs Write Method for Bit-Interleaved Memory Cells,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2011, pp. 325-328, Rio de Janeiro, Brazil, 15-18 May 2011.
• W.G. Ho, K.S. Chong, B.H. Gwee, J.S. Chang, Y. Sun, K.L. Chang, “Improved Asynchronous-Logic Dual-Rail Sense Amplifier-Based Pass Transistor Logic with High Speed and Low Power Operation,” Proceedings of IEEE International Symposium on Circuits and Systems, IEEE ISCAS’2011, pp. 1936-1939, Rio de Janeiro, Brazil, 15-18 May 2011.
• Y. Ren, Y. Shi, B.H. Gwee and C.W. Ting, “An Efficient VLSI Circuit Extraction Algorithm for Transistor-level to Gate-level Abstraction,” Proceedings of Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2010, pp. 49-52, Shanghai, China, pp.49-52, Sep 2010.
• Y. Ren, Y. Shi and B.H. Gwee, “A Novel Gate-level to Behavior-level Conversion Algorithm with High Microcell Identification Rate,” Proceedings of IASTED International Conference on Circuits and Systems, vol. 712, pp. 138, Maui, Hawaii, USA, Aug 2010.
• J. Chen, K.S. Chong, B.H. Gwee and J.S. Chang, “An Ultra-Low Power Asynchronous Quasi-Delay-Insensitive (QDI) Sub-Threshold Memory with Bit-Interleaving and Completion Detection,” Proceedings of IEEE International NEWCAS Conference, NEWCAS’2010, Montreal, Canada, pp. 117–120, 20-23 Jun 2010.
• T. Lin, K.S. Chong, B.H. Gwee, J.S. Chang and Z. Qiu, “Analytical Delay Variation Modeling for Evaluating Sub-Threshold Synchronous/Asynchronous Designs,” Proceedings of IEEE International NEWCAS Conference, NEWCAS’2010, Montreal, Canada, pp. 69-72, 20-23 Jun 2010.
• Y. Shi, C.W. Ting, B.H. Gwee and Y. Ren, “A Highly Efficient Method for Extracting FSMs from Flattened Gate-Level Netlist,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2010, Paris, France, pp. 2610-2613, May 2010.
• T. Ge, J.S. Chang and B.H. Gwee, “Power Supply Noise in High Power-Efficient Open-Loop Class D Amplifiers for Hearing Aid,” Proceedings of IEEE-NIH Circuits and Systems for Medical and Environmental Applications Workshop, Merida, Mexico, Dec 2009.
• N.K. King, J. Liu, K.K. Lee, J.S. Chang, B.H. Gwee, B.T. Ang, “Optimizing Outcome Prediction in Severe Head Injury Using a Two-stage Logistic Regression Method,” Proceedings of World Federation of Neurosurgical Societies Meeting, WFNS’2009, Boston, USA, Aug 2009.
• V. Adrian, J.S. Chang, B.H. Gwee, and S. Tedjaseputro, “Spectral Analysis of Randomized Switching Frequency Modulation Scheme with a Triangular Distribution for DC-DC Converters,” Proceedings of The International Conference of COMPUTING in Engineering, Science and Informatics (ICC2009), pp. 119-122, California, USA, 2-4 Apr 2009.
• K.L. Chang, B.H. Gwee and Y.J. Zhang, “A Performance Benchmark on Asynchronous Matched-Delay Templates,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2009, Taipei, Taiwan, pp. 1008-1011, 24-27 May 2009.
• T. Lin, K.S. Chong, B.H. Gwee and J. Chang, “Fine-Grained Power Gating for Leakage and Short-Circuit Power Reduction by Using Asynchronous-Logic,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2009, Taipei, Taiwan, pp. 3162-3165, 24-27 May 2009.
• K.L. Chang, B.H. Gwee and Y.J. Zhang, “A Semi-Custom Memory Design for an Asynchronous 8051 Microcontroller,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2008, pp. 3398-3401, Seattle, USA, 18-21 May 2008.
• K.L. Chang, Y. Zhu and B.H. Gwee, “De-synchronization of a Point-of-Sales Digital Logic Controller,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2008, pp. 3402-3405, Seattle, USA, 18-24 May 2008.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A simple methodology of designing asynchronous circuits using commercial IC design tools and standard library cells,” Proceedings of International Symposium on Integrated Circuits, ISIC’2007, pp. 176-179, Singapore, 26-28 Sep 2007.
• V. Adrian, B.H. Gwee and J.S. Chang, “A Review of Design Methods for Digital Modulators,” Proceedings of International Symposium on Integrated Circuits, ISIC’2007, pp. 85-88, Singapore, Sep 2007.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A Low Energy FFT/IFFT Processor for Hearing Aids,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2007, pp. 1169-1172, New Orleans, USA, 27-30 May 2007.
• K.L. Chang, B.H. Gwee and Y.J. Zhang, “An Asynchronous Dual-Rail Multiplier Based on Energy-Efficient STFB Templates,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2007, pp. 3267 - 3270, New Orleans, USA, 27-30 May 2007.
• K. Mukherjee and B.H. Gwee, “A 32-Point FFT Based Noise Reduction Algorithm for Single Channel Speech Signals,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2007, pp. 3928 - 3931, New Orleans, USA, 27-30 May 2007.
• Chong-Fatt Law, Bah-Hwee Gwee, and Joseph S. Chang, “Optimized algorithm for computing invariants of ordinary Petri nets,” International Conference on Computer and Information Science, pp. 23-28, Hawaii, United States, 10-12 Jul 2006.
• V. Adrian, B.H. Gwee and J.S. Chang, “An Acoustic Noise Suppression System with Musical Artifacts Reduction,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2006, pp. 2529-2532, Island of Kos, Greece, 21-24 May 2006.
• K.L. Chang and B.H. Gwee, “A Low-Energy Low-Voltage Asynchronous 8051 Microcontroller Core,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2006, pp. 3181-3184, Island of Kos, Greece, 21-24 May 2006.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A Low-Energy Asynchronous FFT/IFFT Processor for Hearing Aid Applications,” Proceedings of IEEE Conference on Electronic Devices and Solid State Circuits, Hong Kong, pp. 751-754, 19-21 Dec 2005.
• Joseph S Chang (NTU), Bah-Hwee Gwee (NTU), Lars Wanhammer (LiU), Kent Palmkvist (LiU), Tapio Saramäki (TUT), Olli Vanio (TUT), Sengprasong Phrakonkham (NUoL), Boulinh Soysouvanh (NUoL), Valasy Chounramany (NUoL) and Saykhong Saynasine (NUoL), “An International Collaboration for the Development of an Online Postgraduate Course on Digital Circuit Technology” Proceedings of 11th International Conference on Technology Supported Learning & Training, Online Educa Berlin, Berlin, Germany, 30th Nov – 2nd Dec 2005.
• V. Adrian, B.H. Gwee and J.S. Chang, “A Combined Interpolatorless Interpolation and High Accuracy Sampling Process for Digital Class D Amplifiers,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2005, pp. 5405-5408, Kobe, Japan, 2005.
• K.S. Chong, B.H. Gwee and J.S. Chang, “Low-Voltage Micropower Multipliers with Reduced Spurious Switching,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2005, pp. 4078-4081, Kobe, Japan, 2005.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A robust low voltage low energy asynchronous carry-completion sensing adder for biomedical applications,” IEEE International Workshop on Biomedical Circuits and Systems, IEEE BioCAS’2004, pp. 18-21, Singapore, Dec 2004.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A Low-Voltage Low Power Accumulator,” Proceedings of International Symposium on Integrated Circuits, Devices and Systems, ISIC’2004, Singapore, 2004.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A Low Power 16-Bit Booth Leapfrog Array Multiplier Using Dynamic Adders,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2004, vol. 2, pp. 437-440, Vancouver, Canada, 2004.
• V. Adrian, B.H. Gwee and J.S. Chang, “A Novel Combined First and Second Order Lagrange Interpolation Sampling Process for a Digital Class D Amplifier,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2004, vol. 3, pp. 233-236, Vancouver, Canada, 2004.
• K.S. Chong, B.H. Gwee and J.S. Chang, “A Critical-Bank Filter Bank based on IFIR and Frequency Response Masking Techniques for Digital Hearing Instruments,” Proceedings of IEEE International Symposium on Consumer Electronics, ISCE’03, paper No. ISCE03053, Sydney, Australia, 2003.
• B.H. Gwee and J.S. Chang, “A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems,” Third International conference on Hybrid Intelligent Systems, HIS'03, Melbourne, Australia, 2003.
• K.H. Chang, B.H. Gwee and J.S. Chang, “A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register File,” International Conference on VLSI, VLSI’03, pp. 166-172, Las Vegas, USA, 2003.
• B.H. Gwee, J.S. Chang, V. Adrian and H. Amir, “A Novel Sampling Process and Pulse Generator for a Low Distortion Digital Pulse-Width Modulator for Digital Class D Amplifiers,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2003, vol. IV, pp. 504-507, Bangkok, Thailand, 2003.
• C.C. Chua, B.H. Gwee and J.S. Chang, “A Low-Voltage Micropower Asynchronous Multiplier for a Multiplierless FIR Filter,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2003 vol. V, pp. 381-384, Bangkok, Thailand, 2003.
• Chong K.S., Gwee B.H. and Chang J.S., “Low-Voltage Asynchronous Multiplier for Hearing Instruments,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2002, vol. 1, pp. 865-868, Arizona, USA, 2002.
• Chong K.S., Gwee B.H. and Chang J.S., “Low-Voltage Asynchronous Adders for Low Power and High Speed Applications,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2002, vol. 1, pp. 873-876, Arizona, USA, 2002.
• Li H.Y., Gwee B.H. and Chang J.S., “A Digital Class D Amplifier Design Embodying a Novel Sampling Process and Pulse Generator,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2001, Sydney, Australia, vol. IV, pp. 826-829, 2001.
• Chang J.S., Gwee B.H. Lon, Y.S. and Tan M.T., “A Novel Low-Power Low-Voltage Class D Amplifier with Feedback for Improving THD, Power Efficiency and Gain Linearity,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2001, Sydney, Australia, vol. I, pp. 635-638, 2001.
• Li H.Y., Gwee B.H., Chang J.S. and Tan M.T., “A Novel Pulse-Width Modulation Sampling Process for Low-Power, Low-Distortion Digital Class D Amplifiers,” Proceedings of IEEE Midwest Symposium on Circuits and Systems, IEEE MWSCAS’2000, vol. 1, pp. 514-517, Michigan, USA, 2000.
• Tan M.T., Chua H.C., Gwee B.H. and Chang J.S., “An Investigation on the Parameters Affecting Total Harmonic Distortion in Class D Amplifiers,” Proceedings of IEEE International Symposium on Circuits and Systems, ISCAS’2000, Geneva, Switzerland, vol. IV, pp. 193-196, 2000.
• Gwee B.H. and Lim M.H., “A GA with Heuristic Based Decoder for Floorplanning with Flexible IC Modules,” Proceedings of International Symposium on Integrated Circuits, Devices and Systems, ISIC'99, Singapore, pp. 451-454, 1999.
• Gwee B.H., Lim M.H. and Soong B.H., “Self-Adjusting Diagnostic System for the Manufacture of Crystal Resonators,” Proceedings of IEEE Industry Application Society Annual Meeting, IAS’93, Toronto, Canada, vol. 3, pp. 2014-2020, 1993.
• Gwee B.H., Lim M.H. and Ho J.S., “Solving Four-Colouring Map Problems using Genetic Algorithm,” Proceedings of International Two-Stream Conference on Artificial Neural Networks and Expert Systems, ANNEZ’93, pp. 322-323, 1993.
• Gwee B.H. and Lim M.H., “Genetic Algorithm for the VLSI Floorplan Design Problem,” Proceedings of International Symposium on IC Design, Manufacture and Applications, ISIC’93, Singapore, pp. 475-479, 1993.
• Lim M.H. and Gwee B.H., “Genetic Algorithms for Solving N-queens Problem,” Proceedings of International Joint Conference on Neural Networks, IJCNN'92, Beijing, China, 1992.
• Lim M.H., Gwee B.H. and Goh T.H., “Cause Associator Network for Fuzzily Deduced Conclusion in Process Control,” Proceedings of IEEE International Joint Conference on Neural Networks, IEEE IJCNN’91, pp. 1248-1253, Nov 1991.
• Gwee B.H. and Lim M.H., “Condition Monitoring of Frequency Trimming Process,” Proceedings of International Symposium on IC Design, Manufacture and Applications, ISIC'91, pp. 220-226, 1991.

Students

Current Students

• Xuenong Hong (PhD candidate, joined in Jan 2020)
• Jun Sheng Ng (PhD candidate, joined in Aug 2019)
• Juncheng Chen (PhD candidate, joined in Aug 2019)
• Deruo Cheng (PhD candidate, joined in Aug 2016)

Former PhD Students

• Ali Akbar Pammu, Thesis Title: Highly Secured and Low Overhead Countermeasures against Side-Channel Attacks (graduated in 2019)
• Keer Cui, Thesis Title: Randomized Modulation Schemes for Digital Modulators of Switched-Mode DC-DC Converters, (graduated in 2018)
• Weng Gang Ho, Ultra Low Power Asynchronous-Logic Quasi-Delay-Insensitive Circuit Design, (graduated in 2016)
• Rong Zhou, Design Methodologies for Robust and Low-Overhead Asynchronous Quasi-Delay-Insensitive (QDI) Digital Systems, (graduated in 2015)
• Tong Lin, Ultra Low-Power Asynchronous-Logic Design for High Variation-Space and Wide Operation-Space Applications, (graduated in 2014)
• Yiqiong Shi, Low Power Asynchronous Digital Signal Processor, (graduated in 2013)
• Kok Leong Chang, Ultra Low-Power Asynchronous-Logic Design for High Variation-Space and Wide Operation-Space Applications, (graduated in 2011)
• Victor Adrian, Modulation Schemes for Digital Modulators of Class D Amplifiers and of Switched-Mode DC-DC Converters, (graduated in 2010)
• Chong Fatt Law, Design Methodologies for Low-Power Asynchronous-Logic Digital Systems, (graduated in 2009
• Kwen Siong Chong, Design and Implementation of a Low Energy FFT/IFFT Processor Based on Asynchronous Logic for Hearing Aid Applications, (graduated in 2007)

Former MEng Students

• Qianqian Liu, High-efficiency Power Amplifier Design for Digital RF Polar Transmitters (graduated in 2017)
• Salma Nashit, Pulse Frequency Modulation for Multi-mode Low-Power Switched-doe DC-DC Converters (graduated in 2016)
• Junchao Chen, Design and Implementation of a Novel Gate-level to Behavior-level Netlist Conversion Tool (graduated in 2013)
• Ye Ren, Design and Implementation of a Novel Gate-level to Behavior-level Netlist Conversion Tool (graduated in 2011
• Chien Chung Chua, Design and Implementation of a Micropower Low Wave Digital Filter Integrated Circuit Based on Asynchronous Logic (graduated in 2003)
• Khia Ho Chang, Low Power Low Voltage IC Design, Asynchronous Circuit Design (graduated in 2003)
• Huiyun Li, Digital Pulse Width Modulator IC For Signal Processing Applications (graduated in 2001)

Invited Talks

• Mar 2020 - Invited Speaker to National Chiao Tung University, Taiwan for Technical Seminar
• Oct 2019 - Invited Speaker to Huazhong University of Science and Technology, Wuhan, China for Technical Seminar
• July 2018 - Invited Speaker to National Tsing Hua University, Taiwan for IEEE Distinguished Lecture
• Jun 2018 - Invited Speaker to Ajou University, South Korea for IEEE Distinguished Lecture
• Jun 2018 - Invited Speaker to Yongsei University, South Korea for Invited Technical Seminar
• Nov 2017 - Invited Speaker to Hanoi National University, Vietnam for IEEE Distinguished Lecture and Workshop Invited Speaker
• Oct 2017 - Invited Speaker to South University of Science and Technology (SUSTec), Shenzhen, China for invited Technical Seminar
• Oct 2017 - Invited Speaker to Hong Kong City University for IEEE Distinguished Lecture
• Jul 2015 - Invited Speaker to University of Electronic Science and Technology of China (UESTC) for Technical Seminar
• Nov 2014 - Invited Speaker to Hong Kong University of Science and Technology (HKUST) for Technical Seminar
• Dec 2010 - Invited Speaker to Royal Melbourne Institute of Technology (RMIT), Australia for IEEE Distinguished Lecture
• Dec 2010 - Invited Speaker to Bilkent University, Turkey for IEEE Distinguished Lecture
• Aug 2010 - Invited Speaker to Qualcomms, Santa Clara Valley, USA for IEEE Distinguished Lecture
• Dec 2009 - Invited Speaker to Beijing University of Post and Telecommunications, China for IEEE Distinguished Lecture
• Oct 2009 - Invited Speaker to Carleton University and Concordia University, Canada for IEEE Distinguished Lectures
• Jul 2009 - Invited Speaker to University Putra Malaysia, Malaysia for IEEE Distinguished Lecture
• Feb 2009 - Invited Speaker of the 1st International Workshop on Circuits and Systems Optimizations and Implementations
• Mar 2008 - Invited to present in Infocomm Technology Seminar organized by Centre of Signal Processing
• Aug 2005 - Invited to present in European Commission Grand-holder Meeting in Philippines
• Jul 2005 - Invited to present in AUNP Asian Workshop in Laos
• § Aug 2004 - Invited to present in AUNP European Workshop in Finland and Sweden
• Aug 1993 - Invited to present in IEEE Singapore Computer Society Technical Seminar

E-learning

• Web-Based E-Learning Portal for Digital Electronics
• Web-Based E-Learning Portal for EE3019 Integrated Electronics
• Web-Based E-Learning Portal for EE6306 Digital Intergrated Circuit Design